// Code generated by 'wasmgen'; DO NOT EDIT.

package ssagen

import (
	"cmd/compile/internal/ir"
	"cmd/compile/internal/ssa"
	"cmd/compile/internal/types"
	"cmd/internal/sys"
)

func initWasmSIMD() {
	makeSimdOp1 := func(op ssa.Op) func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
		return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
			return s.newValue1(op, types.TypeVec128, args[0])
		}
	}
	makeSimdOp2 := func(op ssa.Op) func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
		return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
			return s.newValue2(op, types.TypeVec128, args[0], args[1])
		}
	}
	makeSimdOp3 := func(op ssa.Op) func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
		return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
			return s.newValue3(op, types.TypeVec128, args[0], args[1], args[2])
		}
	}

	// "As" is a type pun, just return the bits
	makeAsOp := func() func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
		return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
			return args[0]
		}
	}

	// converting to a mask is an not-equals comparison with zero, zero obtained by x XOR x.
	makeToMask := func(op, xor ssa.Op) func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
		return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
			return s.newValue2(op, types.TypeVec128, args[0], s.newValue2(xor, n.Type(), args[0], args[0]))
		}
	}

	makeSimdOp1Imm8 := func(op ssa.Op, immLimit uint64) func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
		return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
			t := n.Type()
			if args[1].Op == ssa.OpConst8 && uint64(args[1].AuxInt) < immLimit {
				return s.newValue1I(op, t, args[1].AuxInt, args[0])
			}
			return immJumpTableN(s, args[1], n, immLimit, func(sNew *state, idx int) {
				// Encode as int8 due to requirement of AuxInt, check its comment for details.
				s.vars[n] = sNew.newValue1I(op, t, int64(int8(idx)), args[0])
			})
		}
	}

	makeSimdOp2Imm8 := func(op ssa.Op, immLimit uint64) func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
		return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
			t := types.TypeVec128
			if args[1].Op == ssa.OpConst8 && uint64(args[1].AuxInt) < immLimit {
				return s.newValue2I(op, t, args[1].AuxInt, args[0], args[2])
			}
			return immJumpTableN(s, args[1], n, immLimit, func(sNew *state, idx int) {
				// Encode as int8 due to requirement of AuxInt, check its comment for details.
				s.vars[n] = sNew.newValue2I(op, t, int64(int8(idx)), args[0], args[2])
			})
		}
	}

	addWasmSIMD := func(pkg, fn string, builder func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value) {
		intrinsics.add(sys.ArchWasm, pkg, fn, builder)
	}

	addWasmSIMD("simd/archsimd", "Int8x16.Abs", makeSimdOp1(ssa.OpAbsInt8x16))
	addWasmSIMD("simd/archsimd", "Int16x8.Abs", makeSimdOp1(ssa.OpAbsInt16x8))
	addWasmSIMD("simd/archsimd", "Int32x4.Abs", makeSimdOp1(ssa.OpAbsInt32x4))
	addWasmSIMD("simd/archsimd", "Float32x4.Abs", makeSimdOp1(ssa.OpAbsFloat32x4))
	addWasmSIMD("simd/archsimd", "Int64x2.Abs", makeSimdOp1(ssa.OpAbsInt64x2))
	addWasmSIMD("simd/archsimd", "Float64x2.Abs", makeSimdOp1(ssa.OpAbsFloat64x2))
	addWasmSIMD("simd/archsimd", "Int8x16.Add", makeSimdOp2(ssa.OpAddInt8x16))
	addWasmSIMD("simd/archsimd", "Uint8x16.Add", makeSimdOp2(ssa.OpAddInt8x16))
	addWasmSIMD("simd/archsimd", "Int16x8.Add", makeSimdOp2(ssa.OpAddInt16x8))
	addWasmSIMD("simd/archsimd", "Uint16x8.Add", makeSimdOp2(ssa.OpAddInt16x8))
	addWasmSIMD("simd/archsimd", "Int32x4.Add", makeSimdOp2(ssa.OpAddInt32x4))
	addWasmSIMD("simd/archsimd", "Uint32x4.Add", makeSimdOp2(ssa.OpAddInt32x4))
	addWasmSIMD("simd/archsimd", "Float32x4.Add", makeSimdOp2(ssa.OpAddFloat32x4))
	addWasmSIMD("simd/archsimd", "Int64x2.Add", makeSimdOp2(ssa.OpAddInt64x2))
	addWasmSIMD("simd/archsimd", "Uint64x2.Add", makeSimdOp2(ssa.OpAddInt64x2))
	addWasmSIMD("simd/archsimd", "Float64x2.Add", makeSimdOp2(ssa.OpAddFloat64x2))
	addWasmSIMD("simd/archsimd", "Int8x16.AddSaturated", makeSimdOp2(ssa.OpAddSaturatedInt8x16))
	addWasmSIMD("simd/archsimd", "Uint8x16.AddSaturated", makeSimdOp2(ssa.OpAddSaturatedUint8x16))
	addWasmSIMD("simd/archsimd", "Int16x8.AddSaturated", makeSimdOp2(ssa.OpAddSaturatedInt16x8))
	addWasmSIMD("simd/archsimd", "Uint16x8.AddSaturated", makeSimdOp2(ssa.OpAddSaturatedUint16x8))
	addWasmSIMD("simd/archsimd", "Int8x16.And", makeSimdOp2(ssa.OpAndInt8x16))
	addWasmSIMD("simd/archsimd", "Uint8x16.And", makeSimdOp2(ssa.OpAndUint8x16))
	addWasmSIMD("simd/archsimd", "Mask8x16.And", makeSimdOp2(ssa.OpAndInt8x16))
	addWasmSIMD("simd/archsimd", "Int16x8.And", makeSimdOp2(ssa.OpAndInt16x8))
	addWasmSIMD("simd/archsimd", "Uint16x8.And", makeSimdOp2(ssa.OpAndUint16x8))
	addWasmSIMD("simd/archsimd", "Mask16x8.And", makeSimdOp2(ssa.OpAndInt16x8))
	addWasmSIMD("simd/archsimd", "Int32x4.And", makeSimdOp2(ssa.OpAndInt32x4))
	addWasmSIMD("simd/archsimd", "Uint32x4.And", makeSimdOp2(ssa.OpAndUint32x4))
	addWasmSIMD("simd/archsimd", "Mask32x4.And", makeSimdOp2(ssa.OpAndInt32x4))
	addWasmSIMD("simd/archsimd", "Int64x2.And", makeSimdOp2(ssa.OpAndInt64x2))
	addWasmSIMD("simd/archsimd", "Uint64x2.And", makeSimdOp2(ssa.OpAndUint64x2))
	addWasmSIMD("simd/archsimd", "Mask64x2.And", makeSimdOp2(ssa.OpAndInt64x2))
	addWasmSIMD("simd/archsimd", "Int8x16.AndNot", makeSimdOp2(ssa.OpAndNotInt8x16))
	addWasmSIMD("simd/archsimd", "Uint8x16.AndNot", makeSimdOp2(ssa.OpAndNotUint8x16))
	addWasmSIMD("simd/archsimd", "Mask8x16.AndNot", makeSimdOp2(ssa.OpAndNotInt8x16))
	addWasmSIMD("simd/archsimd", "Int16x8.AndNot", makeSimdOp2(ssa.OpAndNotInt16x8))
	addWasmSIMD("simd/archsimd", "Uint16x8.AndNot", makeSimdOp2(ssa.OpAndNotUint16x8))
	addWasmSIMD("simd/archsimd", "Mask16x8.AndNot", makeSimdOp2(ssa.OpAndNotInt16x8))
	addWasmSIMD("simd/archsimd", "Int32x4.AndNot", makeSimdOp2(ssa.OpAndNotInt32x4))
	addWasmSIMD("simd/archsimd", "Uint32x4.AndNot", makeSimdOp2(ssa.OpAndNotUint32x4))
	addWasmSIMD("simd/archsimd", "Mask32x4.AndNot", makeSimdOp2(ssa.OpAndNotInt32x4))
	addWasmSIMD("simd/archsimd", "Int64x2.AndNot", makeSimdOp2(ssa.OpAndNotInt64x2))
	addWasmSIMD("simd/archsimd", "Uint64x2.AndNot", makeSimdOp2(ssa.OpAndNotUint64x2))
	addWasmSIMD("simd/archsimd", "Mask64x2.AndNot", makeSimdOp2(ssa.OpAndNotInt64x2))
	addWasmSIMD("simd/archsimd", "Uint8x16.Average", makeSimdOp2(ssa.OpAverageUint8x16))
	addWasmSIMD("simd/archsimd", "Uint16x8.Average", makeSimdOp2(ssa.OpAverageUint16x8))
	addWasmSIMD("simd/archsimd", "Int8x16.BitSelect", makeSimdOp3(ssa.OpBitSelectInt8x16))
	addWasmSIMD("simd/archsimd", "Uint8x16.BitSelect", makeSimdOp3(ssa.OpBitSelectUint8x16))
	addWasmSIMD("simd/archsimd", "Int16x8.BitSelect", makeSimdOp3(ssa.OpBitSelectInt16x8))
	addWasmSIMD("simd/archsimd", "Uint16x8.BitSelect", makeSimdOp3(ssa.OpBitSelectUint16x8))
	addWasmSIMD("simd/archsimd", "Int32x4.BitSelect", makeSimdOp3(ssa.OpBitSelectInt32x4))
	addWasmSIMD("simd/archsimd", "Uint32x4.BitSelect", makeSimdOp3(ssa.OpBitSelectUint32x4))
	addWasmSIMD("simd/archsimd", "Int64x2.BitSelect", makeSimdOp3(ssa.OpBitSelectInt64x2))
	addWasmSIMD("simd/archsimd", "Uint64x2.BitSelect", makeSimdOp3(ssa.OpBitSelectUint64x2))
	addWasmSIMD("simd/archsimd", "Float32x4.Ceil", makeSimdOp1(ssa.OpCeilFloat32x4))
	addWasmSIMD("simd/archsimd", "Float64x2.Ceil", makeSimdOp1(ssa.OpCeilFloat64x2))
	addWasmSIMD("simd/archsimd", "Int32x4.ConvertLo2ToFloat64", makeSimdOp1(ssa.OpConvertLo2ToFloat64Int32x4))
	addWasmSIMD("simd/archsimd", "Uint32x4.ConvertLo2ToFloat64", makeSimdOp1(ssa.OpConvertLo2ToFloat64Uint32x4))
	addWasmSIMD("simd/archsimd", "Int32x4.ConvertToFloat32", makeSimdOp1(ssa.OpConvertToFloat32Int32x4))
	addWasmSIMD("simd/archsimd", "Uint32x4.ConvertToFloat32", makeSimdOp1(ssa.OpConvertToFloat32Uint32x4))
	addWasmSIMD("simd/archsimd", "Float32x4.ConvertToInt32", makeSimdOp1(ssa.OpConvertToInt32Float32x4))
	addWasmSIMD("simd/archsimd", "Float32x4.ConvertToUint32", makeSimdOp1(ssa.OpConvertToUint32Float32x4))
	addWasmSIMD("simd/archsimd", "Float32x4.Div", makeSimdOp2(ssa.OpDivFloat32x4))
	addWasmSIMD("simd/archsimd", "Float64x2.Div", makeSimdOp2(ssa.OpDivFloat64x2))
	addWasmSIMD("simd/archsimd", "Int8x16.Equal", makeSimdOp2(ssa.OpEqualInt8x16))
	addWasmSIMD("simd/archsimd", "Uint8x16.Equal", makeSimdOp2(ssa.OpEqualUint8x16))
	addWasmSIMD("simd/archsimd", "Int16x8.Equal", makeSimdOp2(ssa.OpEqualInt16x8))
	addWasmSIMD("simd/archsimd", "Uint16x8.Equal", makeSimdOp2(ssa.OpEqualUint16x8))
	addWasmSIMD("simd/archsimd", "Int32x4.Equal", makeSimdOp2(ssa.OpEqualInt32x4))
	addWasmSIMD("simd/archsimd", "Uint32x4.Equal", makeSimdOp2(ssa.OpEqualUint32x4))
	addWasmSIMD("simd/archsimd", "Float32x4.Equal", makeSimdOp2(ssa.OpEqualFloat32x4))
	addWasmSIMD("simd/archsimd", "Int64x2.Equal", makeSimdOp2(ssa.OpEqualInt64x2))
	addWasmSIMD("simd/archsimd", "Uint64x2.Equal", makeSimdOp2(ssa.OpEqualUint64x2))
	addWasmSIMD("simd/archsimd", "Float64x2.Equal", makeSimdOp2(ssa.OpEqualFloat64x2))
	addWasmSIMD("simd/archsimd", "Int32x4.ExtendHi2ToInt64", makeSimdOp1(ssa.OpExtendHi2ToInt64Int32x4))
	addWasmSIMD("simd/archsimd", "Uint32x4.ExtendHi2ToUint64", makeSimdOp1(ssa.OpExtendHi2ToUint64Uint32x4))
	addWasmSIMD("simd/archsimd", "Int16x8.ExtendHi4ToInt32", makeSimdOp1(ssa.OpExtendHi4ToInt32Int16x8))
	addWasmSIMD("simd/archsimd", "Uint16x8.ExtendHi4ToUint32", makeSimdOp1(ssa.OpExtendHi4ToUint32Uint16x8))
	addWasmSIMD("simd/archsimd", "Int8x16.ExtendHi8ToInt16", makeSimdOp1(ssa.OpExtendHi8ToInt16Int8x16))
	addWasmSIMD("simd/archsimd", "Uint8x16.ExtendHi8ToUint16", makeSimdOp1(ssa.OpExtendHi8ToUint16Uint8x16))
	addWasmSIMD("simd/archsimd", "Int32x4.ExtendLo2ToInt64", makeSimdOp1(ssa.OpExtendLo2ToInt64Int32x4))
	addWasmSIMD("simd/archsimd", "Uint32x4.ExtendLo2ToUint64", makeSimdOp1(ssa.OpExtendLo2ToUint64Uint32x4))
	addWasmSIMD("simd/archsimd", "Int16x8.ExtendLo4ToInt32", makeSimdOp1(ssa.OpExtendLo4ToInt32Int16x8))
	addWasmSIMD("simd/archsimd", "Uint16x8.ExtendLo4ToUint32", makeSimdOp1(ssa.OpExtendLo4ToUint32Uint16x8))
	addWasmSIMD("simd/archsimd", "Int8x16.ExtendLo8ToInt16", makeSimdOp1(ssa.OpExtendLo8ToInt16Int8x16))
	addWasmSIMD("simd/archsimd", "Uint8x16.ExtendLo8ToUint16", makeSimdOp1(ssa.OpExtendLo8ToUint16Uint8x16))
	addWasmSIMD("simd/archsimd", "Float32x4.Floor", makeSimdOp1(ssa.OpFloorFloat32x4))
	addWasmSIMD("simd/archsimd", "Float64x2.Floor", makeSimdOp1(ssa.OpFloorFloat64x2))
	addWasmSIMD("simd/archsimd", "Int8x16.GetElem", makeSimdOp1Imm8(ssa.OpGetElemInt8x16, 16))
	addWasmSIMD("simd/archsimd", "Uint8x16.GetElem", makeSimdOp1Imm8(ssa.OpGetElemUint8x16, 16))
	addWasmSIMD("simd/archsimd", "Int16x8.GetElem", makeSimdOp1Imm8(ssa.OpGetElemInt16x8, 8))
	addWasmSIMD("simd/archsimd", "Uint16x8.GetElem", makeSimdOp1Imm8(ssa.OpGetElemUint16x8, 8))
	addWasmSIMD("simd/archsimd", "Int32x4.GetElem", makeSimdOp1Imm8(ssa.OpGetElemInt32x4, 4))
	addWasmSIMD("simd/archsimd", "Uint32x4.GetElem", makeSimdOp1Imm8(ssa.OpGetElemUint32x4, 4))
	addWasmSIMD("simd/archsimd", "Float32x4.GetElem", makeSimdOp1Imm8(ssa.OpGetElemFloat32x4, 4))
	addWasmSIMD("simd/archsimd", "Int64x2.GetElem", makeSimdOp1Imm8(ssa.OpGetElemInt64x2, 2))
	addWasmSIMD("simd/archsimd", "Uint64x2.GetElem", makeSimdOp1Imm8(ssa.OpGetElemUint64x2, 2))
	addWasmSIMD("simd/archsimd", "Float64x2.GetElem", makeSimdOp1Imm8(ssa.OpGetElemFloat64x2, 2))
	addWasmSIMD("simd/archsimd", "Int8x16.Greater", makeSimdOp2(ssa.OpGreaterInt8x16))
	addWasmSIMD("simd/archsimd", "Uint8x16.Greater", makeSimdOp2(ssa.OpGreaterUint8x16))
	addWasmSIMD("simd/archsimd", "Int16x8.Greater", makeSimdOp2(ssa.OpGreaterInt16x8))
	addWasmSIMD("simd/archsimd", "Uint16x8.Greater", makeSimdOp2(ssa.OpGreaterUint16x8))
	addWasmSIMD("simd/archsimd", "Int32x4.Greater", makeSimdOp2(ssa.OpGreaterInt32x4))
	addWasmSIMD("simd/archsimd", "Uint32x4.Greater", makeSimdOp2(ssa.OpGreaterUint32x4))
	addWasmSIMD("simd/archsimd", "Float32x4.Greater", makeSimdOp2(ssa.OpGreaterFloat32x4))
	addWasmSIMD("simd/archsimd", "Int64x2.Greater", makeSimdOp2(ssa.OpGreaterInt64x2))
	addWasmSIMD("simd/archsimd", "Float64x2.Greater", makeSimdOp2(ssa.OpGreaterFloat64x2))
	addWasmSIMD("simd/archsimd", "Int8x16.GreaterEqual", makeSimdOp2(ssa.OpGreaterEqualInt8x16))
	addWasmSIMD("simd/archsimd", "Uint8x16.GreaterEqual", makeSimdOp2(ssa.OpGreaterEqualUint8x16))
	addWasmSIMD("simd/archsimd", "Int16x8.GreaterEqual", makeSimdOp2(ssa.OpGreaterEqualInt16x8))
	addWasmSIMD("simd/archsimd", "Uint16x8.GreaterEqual", makeSimdOp2(ssa.OpGreaterEqualUint16x8))
	addWasmSIMD("simd/archsimd", "Int32x4.GreaterEqual", makeSimdOp2(ssa.OpGreaterEqualInt32x4))
	addWasmSIMD("simd/archsimd", "Uint32x4.GreaterEqual", makeSimdOp2(ssa.OpGreaterEqualUint32x4))
	addWasmSIMD("simd/archsimd", "Float32x4.GreaterEqual", makeSimdOp2(ssa.OpGreaterEqualFloat32x4))
	addWasmSIMD("simd/archsimd", "Int64x2.GreaterEqual", makeSimdOp2(ssa.OpGreaterEqualInt64x2))
	addWasmSIMD("simd/archsimd", "Float64x2.GreaterEqual", makeSimdOp2(ssa.OpGreaterEqualFloat64x2))
	addWasmSIMD("simd/archsimd", "Int8x16.Less", makeSimdOp2(ssa.OpLessInt8x16))
	addWasmSIMD("simd/archsimd", "Uint8x16.Less", makeSimdOp2(ssa.OpLessUint8x16))
	addWasmSIMD("simd/archsimd", "Int16x8.Less", makeSimdOp2(ssa.OpLessInt16x8))
	addWasmSIMD("simd/archsimd", "Uint16x8.Less", makeSimdOp2(ssa.OpLessUint16x8))
	addWasmSIMD("simd/archsimd", "Int32x4.Less", makeSimdOp2(ssa.OpLessInt32x4))
	addWasmSIMD("simd/archsimd", "Uint32x4.Less", makeSimdOp2(ssa.OpLessUint32x4))
	addWasmSIMD("simd/archsimd", "Float32x4.Less", makeSimdOp2(ssa.OpLessFloat32x4))
	addWasmSIMD("simd/archsimd", "Int64x2.Less", makeSimdOp2(ssa.OpLessInt64x2))
	addWasmSIMD("simd/archsimd", "Float64x2.Less", makeSimdOp2(ssa.OpLessFloat64x2))
	addWasmSIMD("simd/archsimd", "Int8x16.LessEqual", makeSimdOp2(ssa.OpLessEqualInt8x16))
	addWasmSIMD("simd/archsimd", "Uint8x16.LessEqual", makeSimdOp2(ssa.OpLessEqualUint8x16))
	addWasmSIMD("simd/archsimd", "Int16x8.LessEqual", makeSimdOp2(ssa.OpLessEqualInt16x8))
	addWasmSIMD("simd/archsimd", "Uint16x8.LessEqual", makeSimdOp2(ssa.OpLessEqualUint16x8))
	addWasmSIMD("simd/archsimd", "Int32x4.LessEqual", makeSimdOp2(ssa.OpLessEqualInt32x4))
	addWasmSIMD("simd/archsimd", "Uint32x4.LessEqual", makeSimdOp2(ssa.OpLessEqualUint32x4))
	addWasmSIMD("simd/archsimd", "Float32x4.LessEqual", makeSimdOp2(ssa.OpLessEqualFloat32x4))
	addWasmSIMD("simd/archsimd", "Int64x2.LessEqual", makeSimdOp2(ssa.OpLessEqualInt64x2))
	addWasmSIMD("simd/archsimd", "Float64x2.LessEqual", makeSimdOp2(ssa.OpLessEqualFloat64x2))
	addWasmSIMD("simd/archsimd", "Int8x16.LookupOrZero", makeSimdOp2(ssa.OpLookupOrZeroInt8x16))
	addWasmSIMD("simd/archsimd", "Int8x16.Max", makeSimdOp2(ssa.OpMaxInt8x16))
	addWasmSIMD("simd/archsimd", "Uint8x16.Max", makeSimdOp2(ssa.OpMaxUint8x16))
	addWasmSIMD("simd/archsimd", "Int16x8.Max", makeSimdOp2(ssa.OpMaxInt16x8))
	addWasmSIMD("simd/archsimd", "Uint16x8.Max", makeSimdOp2(ssa.OpMaxUint16x8))
	addWasmSIMD("simd/archsimd", "Int32x4.Max", makeSimdOp2(ssa.OpMaxInt32x4))
	addWasmSIMD("simd/archsimd", "Uint32x4.Max", makeSimdOp2(ssa.OpMaxUint32x4))
	addWasmSIMD("simd/archsimd", "Float32x4.Max", makeSimdOp2(ssa.OpMaxFloat32x4))
	addWasmSIMD("simd/archsimd", "Float64x2.Max", makeSimdOp2(ssa.OpMaxFloat64x2))
	addWasmSIMD("simd/archsimd", "Int8x16.Min", makeSimdOp2(ssa.OpMinInt8x16))
	addWasmSIMD("simd/archsimd", "Uint8x16.Min", makeSimdOp2(ssa.OpMinUint8x16))
	addWasmSIMD("simd/archsimd", "Int16x8.Min", makeSimdOp2(ssa.OpMinInt16x8))
	addWasmSIMD("simd/archsimd", "Uint16x8.Min", makeSimdOp2(ssa.OpMinUint16x8))
	addWasmSIMD("simd/archsimd", "Int32x4.Min", makeSimdOp2(ssa.OpMinInt32x4))
	addWasmSIMD("simd/archsimd", "Uint32x4.Min", makeSimdOp2(ssa.OpMinUint32x4))
	addWasmSIMD("simd/archsimd", "Float32x4.Min", makeSimdOp2(ssa.OpMinFloat32x4))
	addWasmSIMD("simd/archsimd", "Float64x2.Min", makeSimdOp2(ssa.OpMinFloat64x2))
	addWasmSIMD("simd/archsimd", "Int16x8.Mul", makeSimdOp2(ssa.OpMulInt16x8))
	addWasmSIMD("simd/archsimd", "Uint16x8.Mul", makeSimdOp2(ssa.OpMulUint16x8))
	addWasmSIMD("simd/archsimd", "Int32x4.Mul", makeSimdOp2(ssa.OpMulInt32x4))
	addWasmSIMD("simd/archsimd", "Uint32x4.Mul", makeSimdOp2(ssa.OpMulUint32x4))
	addWasmSIMD("simd/archsimd", "Float32x4.Mul", makeSimdOp2(ssa.OpMulFloat32x4))
	addWasmSIMD("simd/archsimd", "Int64x2.Mul", makeSimdOp2(ssa.OpMulInt64x2))
	addWasmSIMD("simd/archsimd", "Uint64x2.Mul", makeSimdOp2(ssa.OpMulUint64x2))
	addWasmSIMD("simd/archsimd", "Float64x2.Mul", makeSimdOp2(ssa.OpMulFloat64x2))
	addWasmSIMD("simd/archsimd", "Int8x16.MulWidenHi", makeSimdOp2(ssa.OpMulWidenHiInt8x16))
	addWasmSIMD("simd/archsimd", "Uint8x16.MulWidenHi", makeSimdOp2(ssa.OpMulWidenHiUint8x16))
	addWasmSIMD("simd/archsimd", "Int16x8.MulWidenHi", makeSimdOp2(ssa.OpMulWidenHiInt16x8))
	addWasmSIMD("simd/archsimd", "Uint16x8.MulWidenHi", makeSimdOp2(ssa.OpMulWidenHiUint16x8))
	addWasmSIMD("simd/archsimd", "Int32x4.MulWidenHi", makeSimdOp2(ssa.OpMulWidenHiInt32x4))
	addWasmSIMD("simd/archsimd", "Uint32x4.MulWidenHi", makeSimdOp2(ssa.OpMulWidenHiUint32x4))
	addWasmSIMD("simd/archsimd", "Int8x16.MulWidenLo", makeSimdOp2(ssa.OpMulWidenLoInt8x16))
	addWasmSIMD("simd/archsimd", "Uint8x16.MulWidenLo", makeSimdOp2(ssa.OpMulWidenLoUint8x16))
	addWasmSIMD("simd/archsimd", "Int16x8.MulWidenLo", makeSimdOp2(ssa.OpMulWidenLoInt16x8))
	addWasmSIMD("simd/archsimd", "Uint16x8.MulWidenLo", makeSimdOp2(ssa.OpMulWidenLoUint16x8))
	addWasmSIMD("simd/archsimd", "Int32x4.MulWidenLo", makeSimdOp2(ssa.OpMulWidenLoInt32x4))
	addWasmSIMD("simd/archsimd", "Uint32x4.MulWidenLo", makeSimdOp2(ssa.OpMulWidenLoUint32x4))
	addWasmSIMD("simd/archsimd", "Int8x16.Neg", makeSimdOp1(ssa.OpNegInt8x16))
	addWasmSIMD("simd/archsimd", "Int16x8.Neg", makeSimdOp1(ssa.OpNegInt16x8))
	addWasmSIMD("simd/archsimd", "Int32x4.Neg", makeSimdOp1(ssa.OpNegInt32x4))
	addWasmSIMD("simd/archsimd", "Float32x4.Neg", makeSimdOp1(ssa.OpNegFloat32x4))
	addWasmSIMD("simd/archsimd", "Int64x2.Neg", makeSimdOp1(ssa.OpNegInt64x2))
	addWasmSIMD("simd/archsimd", "Float64x2.Neg", makeSimdOp1(ssa.OpNegFloat64x2))
	addWasmSIMD("simd/archsimd", "Int8x16.Not", makeSimdOp1(ssa.OpNotInt8x16))
	addWasmSIMD("simd/archsimd", "Uint8x16.Not", makeSimdOp1(ssa.OpNotUint8x16))
	addWasmSIMD("simd/archsimd", "Int16x8.Not", makeSimdOp1(ssa.OpNotInt16x8))
	addWasmSIMD("simd/archsimd", "Uint16x8.Not", makeSimdOp1(ssa.OpNotUint16x8))
	addWasmSIMD("simd/archsimd", "Int32x4.Not", makeSimdOp1(ssa.OpNotInt32x4))
	addWasmSIMD("simd/archsimd", "Uint32x4.Not", makeSimdOp1(ssa.OpNotUint32x4))
	addWasmSIMD("simd/archsimd", "Int64x2.Not", makeSimdOp1(ssa.OpNotInt64x2))
	addWasmSIMD("simd/archsimd", "Uint64x2.Not", makeSimdOp1(ssa.OpNotUint64x2))
	addWasmSIMD("simd/archsimd", "Int8x16.NotEqual", makeSimdOp2(ssa.OpNotEqualInt8x16))
	addWasmSIMD("simd/archsimd", "Uint8x16.NotEqual", makeSimdOp2(ssa.OpNotEqualUint8x16))
	addWasmSIMD("simd/archsimd", "Int16x8.NotEqual", makeSimdOp2(ssa.OpNotEqualInt16x8))
	addWasmSIMD("simd/archsimd", "Uint16x8.NotEqual", makeSimdOp2(ssa.OpNotEqualUint16x8))
	addWasmSIMD("simd/archsimd", "Int32x4.NotEqual", makeSimdOp2(ssa.OpNotEqualInt32x4))
	addWasmSIMD("simd/archsimd", "Uint32x4.NotEqual", makeSimdOp2(ssa.OpNotEqualUint32x4))
	addWasmSIMD("simd/archsimd", "Float32x4.NotEqual", makeSimdOp2(ssa.OpNotEqualFloat32x4))
	addWasmSIMD("simd/archsimd", "Int64x2.NotEqual", makeSimdOp2(ssa.OpNotEqualInt64x2))
	addWasmSIMD("simd/archsimd", "Uint64x2.NotEqual", makeSimdOp2(ssa.OpNotEqualUint64x2))
	addWasmSIMD("simd/archsimd", "Float64x2.NotEqual", makeSimdOp2(ssa.OpNotEqualFloat64x2))
	addWasmSIMD("simd/archsimd", "Int8x16.OnesCount", makeSimdOp1(ssa.OpOnesCountInt8x16))
	addWasmSIMD("simd/archsimd", "Int8x16.Or", makeSimdOp2(ssa.OpOrInt8x16))
	addWasmSIMD("simd/archsimd", "Uint8x16.Or", makeSimdOp2(ssa.OpOrUint8x16))
	addWasmSIMD("simd/archsimd", "Mask8x16.Or", makeSimdOp2(ssa.OpOrInt8x16))
	addWasmSIMD("simd/archsimd", "Int16x8.Or", makeSimdOp2(ssa.OpOrInt16x8))
	addWasmSIMD("simd/archsimd", "Uint16x8.Or", makeSimdOp2(ssa.OpOrUint16x8))
	addWasmSIMD("simd/archsimd", "Mask16x8.Or", makeSimdOp2(ssa.OpOrInt16x8))
	addWasmSIMD("simd/archsimd", "Int32x4.Or", makeSimdOp2(ssa.OpOrInt32x4))
	addWasmSIMD("simd/archsimd", "Uint32x4.Or", makeSimdOp2(ssa.OpOrUint32x4))
	addWasmSIMD("simd/archsimd", "Mask32x4.Or", makeSimdOp2(ssa.OpOrInt32x4))
	addWasmSIMD("simd/archsimd", "Int64x2.Or", makeSimdOp2(ssa.OpOrInt64x2))
	addWasmSIMD("simd/archsimd", "Uint64x2.Or", makeSimdOp2(ssa.OpOrUint64x2))
	addWasmSIMD("simd/archsimd", "Mask64x2.Or", makeSimdOp2(ssa.OpOrInt64x2))
	addWasmSIMD("simd/archsimd", "Int8x16.RotateAllLeft", makeSimdOp2(ssa.OpRotateAllLeftVarInt8x16))
	addWasmSIMD("simd/archsimd", "Uint8x16.RotateAllLeft", makeSimdOp2(ssa.OpRotateAllLeftVarUint8x16))
	addWasmSIMD("simd/archsimd", "Int16x8.RotateAllLeft", makeSimdOp2(ssa.OpRotateAllLeftVarInt16x8))
	addWasmSIMD("simd/archsimd", "Uint16x8.RotateAllLeft", makeSimdOp2(ssa.OpRotateAllLeftVarUint16x8))
	addWasmSIMD("simd/archsimd", "Int32x4.RotateAllLeft", makeSimdOp2(ssa.OpRotateAllLeftVarInt32x4))
	addWasmSIMD("simd/archsimd", "Uint32x4.RotateAllLeft", makeSimdOp2(ssa.OpRotateAllLeftVarUint32x4))
	addWasmSIMD("simd/archsimd", "Int64x2.RotateAllLeft", makeSimdOp2(ssa.OpRotateAllLeftVarInt64x2))
	addWasmSIMD("simd/archsimd", "Uint64x2.RotateAllLeft", makeSimdOp2(ssa.OpRotateAllLeftVarUint64x2))
	addWasmSIMD("simd/archsimd", "Int8x16.RotateAllRight", makeSimdOp2(ssa.OpRotateAllRightVarInt8x16))
	addWasmSIMD("simd/archsimd", "Uint8x16.RotateAllRight", makeSimdOp2(ssa.OpRotateAllRightVarUint8x16))
	addWasmSIMD("simd/archsimd", "Int16x8.RotateAllRight", makeSimdOp2(ssa.OpRotateAllRightVarInt16x8))
	addWasmSIMD("simd/archsimd", "Uint16x8.RotateAllRight", makeSimdOp2(ssa.OpRotateAllRightVarUint16x8))
	addWasmSIMD("simd/archsimd", "Int32x4.RotateAllRight", makeSimdOp2(ssa.OpRotateAllRightVarInt32x4))
	addWasmSIMD("simd/archsimd", "Uint32x4.RotateAllRight", makeSimdOp2(ssa.OpRotateAllRightVarUint32x4))
	addWasmSIMD("simd/archsimd", "Int64x2.RotateAllRight", makeSimdOp2(ssa.OpRotateAllRightVarInt64x2))
	addWasmSIMD("simd/archsimd", "Uint64x2.RotateAllRight", makeSimdOp2(ssa.OpRotateAllRightVarUint64x2))
	addWasmSIMD("simd/archsimd", "Float32x4.Round", makeSimdOp1(ssa.OpRoundFloat32x4))
	addWasmSIMD("simd/archsimd", "Float64x2.Round", makeSimdOp1(ssa.OpRoundFloat64x2))
	addWasmSIMD("simd/archsimd", "Int8x16.SetElem", makeSimdOp2Imm8(ssa.OpSetElemInt8x16, 16))
	addWasmSIMD("simd/archsimd", "Uint8x16.SetElem", makeSimdOp2Imm8(ssa.OpSetElemUint8x16, 16))
	addWasmSIMD("simd/archsimd", "Int16x8.SetElem", makeSimdOp2Imm8(ssa.OpSetElemInt16x8, 8))
	addWasmSIMD("simd/archsimd", "Uint16x8.SetElem", makeSimdOp2Imm8(ssa.OpSetElemUint16x8, 8))
	addWasmSIMD("simd/archsimd", "Int32x4.SetElem", makeSimdOp2Imm8(ssa.OpSetElemInt32x4, 4))
	addWasmSIMD("simd/archsimd", "Uint32x4.SetElem", makeSimdOp2Imm8(ssa.OpSetElemUint32x4, 4))
	addWasmSIMD("simd/archsimd", "Float32x4.SetElem", makeSimdOp2Imm8(ssa.OpSetElemFloat32x4, 4))
	addWasmSIMD("simd/archsimd", "Int64x2.SetElem", makeSimdOp2Imm8(ssa.OpSetElemInt64x2, 2))
	addWasmSIMD("simd/archsimd", "Uint64x2.SetElem", makeSimdOp2Imm8(ssa.OpSetElemUint64x2, 2))
	addWasmSIMD("simd/archsimd", "Float64x2.SetElem", makeSimdOp2Imm8(ssa.OpSetElemFloat64x2, 2))
	addWasmSIMD("simd/archsimd", "Int8x16.ShiftAllLeft", makeSimdOp2(ssa.OpShiftAllLeftInt8x16))
	addWasmSIMD("simd/archsimd", "Uint8x16.ShiftAllLeft", makeSimdOp2(ssa.OpShiftAllLeftUint8x16))
	addWasmSIMD("simd/archsimd", "Int16x8.ShiftAllLeft", makeSimdOp2(ssa.OpShiftAllLeftInt16x8))
	addWasmSIMD("simd/archsimd", "Uint16x8.ShiftAllLeft", makeSimdOp2(ssa.OpShiftAllLeftUint16x8))
	addWasmSIMD("simd/archsimd", "Int32x4.ShiftAllLeft", makeSimdOp2(ssa.OpShiftAllLeftInt32x4))
	addWasmSIMD("simd/archsimd", "Uint32x4.ShiftAllLeft", makeSimdOp2(ssa.OpShiftAllLeftUint32x4))
	addWasmSIMD("simd/archsimd", "Int64x2.ShiftAllLeft", makeSimdOp2(ssa.OpShiftAllLeftInt64x2))
	addWasmSIMD("simd/archsimd", "Uint64x2.ShiftAllLeft", makeSimdOp2(ssa.OpShiftAllLeftUint64x2))
	addWasmSIMD("simd/archsimd", "Int8x16.ShiftAllRight", makeSimdOp2(ssa.OpShiftAllRightInt8x16))
	addWasmSIMD("simd/archsimd", "Uint8x16.ShiftAllRight", makeSimdOp2(ssa.OpShiftAllRightUint8x16))
	addWasmSIMD("simd/archsimd", "Int16x8.ShiftAllRight", makeSimdOp2(ssa.OpShiftAllRightInt16x8))
	addWasmSIMD("simd/archsimd", "Uint16x8.ShiftAllRight", makeSimdOp2(ssa.OpShiftAllRightUint16x8))
	addWasmSIMD("simd/archsimd", "Int32x4.ShiftAllRight", makeSimdOp2(ssa.OpShiftAllRightInt32x4))
	addWasmSIMD("simd/archsimd", "Uint32x4.ShiftAllRight", makeSimdOp2(ssa.OpShiftAllRightUint32x4))
	addWasmSIMD("simd/archsimd", "Int64x2.ShiftAllRight", makeSimdOp2(ssa.OpShiftAllRightInt64x2))
	addWasmSIMD("simd/archsimd", "Uint64x2.ShiftAllRight", makeSimdOp2(ssa.OpShiftAllRightUint64x2))
	addWasmSIMD("simd/archsimd", "Float32x4.Sqrt", makeSimdOp1(ssa.OpSqrtFloat32x4))
	addWasmSIMD("simd/archsimd", "Float64x2.Sqrt", makeSimdOp1(ssa.OpSqrtFloat64x2))
	addWasmSIMD("simd/archsimd", "Int8x16.Sub", makeSimdOp2(ssa.OpSubInt8x16))
	addWasmSIMD("simd/archsimd", "Uint8x16.Sub", makeSimdOp2(ssa.OpSubInt8x16))
	addWasmSIMD("simd/archsimd", "Int16x8.Sub", makeSimdOp2(ssa.OpSubInt16x8))
	addWasmSIMD("simd/archsimd", "Uint16x8.Sub", makeSimdOp2(ssa.OpSubInt16x8))
	addWasmSIMD("simd/archsimd", "Int32x4.Sub", makeSimdOp2(ssa.OpSubInt32x4))
	addWasmSIMD("simd/archsimd", "Uint32x4.Sub", makeSimdOp2(ssa.OpSubInt32x4))
	addWasmSIMD("simd/archsimd", "Float32x4.Sub", makeSimdOp2(ssa.OpSubFloat32x4))
	addWasmSIMD("simd/archsimd", "Int64x2.Sub", makeSimdOp2(ssa.OpSubInt64x2))
	addWasmSIMD("simd/archsimd", "Uint64x2.Sub", makeSimdOp2(ssa.OpSubInt64x2))
	addWasmSIMD("simd/archsimd", "Float64x2.Sub", makeSimdOp2(ssa.OpSubFloat64x2))
	addWasmSIMD("simd/archsimd", "Int8x16.SubSaturated", makeSimdOp2(ssa.OpSubSaturatedInt8x16))
	addWasmSIMD("simd/archsimd", "Uint8x16.SubSaturated", makeSimdOp2(ssa.OpSubSaturatedUint8x16))
	addWasmSIMD("simd/archsimd", "Int16x8.SubSaturated", makeSimdOp2(ssa.OpSubSaturatedInt16x8))
	addWasmSIMD("simd/archsimd", "Uint16x8.SubSaturated", makeSimdOp2(ssa.OpSubSaturatedUint16x8))
	addWasmSIMD("simd/archsimd", "Float32x4.Trunc", makeSimdOp1(ssa.OpTruncFloat32x4))
	addWasmSIMD("simd/archsimd", "Float64x2.Trunc", makeSimdOp1(ssa.OpTruncFloat64x2))
	addWasmSIMD("simd/archsimd", "Int8x16.Xor", makeSimdOp2(ssa.OpXorInt8x16))
	addWasmSIMD("simd/archsimd", "Uint8x16.Xor", makeSimdOp2(ssa.OpXorUint8x16))
	addWasmSIMD("simd/archsimd", "Mask8x16.Xor", makeSimdOp2(ssa.OpXorInt8x16))
	addWasmSIMD("simd/archsimd", "Int16x8.Xor", makeSimdOp2(ssa.OpXorInt16x8))
	addWasmSIMD("simd/archsimd", "Uint16x8.Xor", makeSimdOp2(ssa.OpXorUint16x8))
	addWasmSIMD("simd/archsimd", "Mask16x8.Xor", makeSimdOp2(ssa.OpXorInt16x8))
	addWasmSIMD("simd/archsimd", "Int32x4.Xor", makeSimdOp2(ssa.OpXorInt32x4))
	addWasmSIMD("simd/archsimd", "Uint32x4.Xor", makeSimdOp2(ssa.OpXorUint32x4))
	addWasmSIMD("simd/archsimd", "Mask32x4.Xor", makeSimdOp2(ssa.OpXorInt32x4))
	addWasmSIMD("simd/archsimd", "Int64x2.Xor", makeSimdOp2(ssa.OpXorInt64x2))
	addWasmSIMD("simd/archsimd", "Uint64x2.Xor", makeSimdOp2(ssa.OpXorUint64x2))
	addWasmSIMD("simd/archsimd", "Mask64x2.Xor", makeSimdOp2(ssa.OpXorInt64x2))
	addWasmSIMD("simd/archsimd", "Int8x16.ToMask", makeToMask(ssa.OpNotEqualInt8x16, ssa.OpXorInt8x16))
	addWasmSIMD("simd/archsimd", "Mask8x16.ToInt8x16", makeAsOp())
	addWasmSIMD("simd/archsimd", "Int16x8.ToMask", makeToMask(ssa.OpNotEqualInt16x8, ssa.OpXorInt16x8))
	addWasmSIMD("simd/archsimd", "Mask16x8.ToInt16x8", makeAsOp())
	addWasmSIMD("simd/archsimd", "Int32x4.ToMask", makeToMask(ssa.OpNotEqualInt32x4, ssa.OpXorInt32x4))
	addWasmSIMD("simd/archsimd", "Mask32x4.ToInt32x4", makeAsOp())
	addWasmSIMD("simd/archsimd", "Int64x2.ToMask", makeToMask(ssa.OpNotEqualInt64x2, ssa.OpXorInt64x2))
	addWasmSIMD("simd/archsimd", "Mask64x2.ToInt64x2", makeAsOp())
	addWasmSIMD("simd/archsimd", "LoadInt8x16Array", simdLoad())
	addWasmSIMD("simd/archsimd", "BroadcastInt8x16", simdBroadcast(ssa.OpBroadcastInt8x16))
	addWasmSIMD("simd/archsimd", "Int8x16.StoreArray", simdStore())
	addWasmSIMD("simd/archsimd", "LoadInt16x8Array", simdLoad())
	addWasmSIMD("simd/archsimd", "BroadcastInt16x8", simdBroadcast(ssa.OpBroadcastInt16x8))
	addWasmSIMD("simd/archsimd", "Int16x8.StoreArray", simdStore())
	addWasmSIMD("simd/archsimd", "LoadInt32x4Array", simdLoad())
	addWasmSIMD("simd/archsimd", "BroadcastInt32x4", simdBroadcast(ssa.OpBroadcastInt32x4))
	addWasmSIMD("simd/archsimd", "Int32x4.StoreArray", simdStore())
	addWasmSIMD("simd/archsimd", "LoadInt64x2Array", simdLoad())
	addWasmSIMD("simd/archsimd", "BroadcastInt64x2", simdBroadcast(ssa.OpBroadcastInt64x2))
	addWasmSIMD("simd/archsimd", "Int64x2.StoreArray", simdStore())
	addWasmSIMD("simd/archsimd", "LoadUint8x16Array", simdLoad())
	addWasmSIMD("simd/archsimd", "BroadcastUint8x16", simdBroadcast(ssa.OpBroadcastInt8x16))
	addWasmSIMD("simd/archsimd", "Uint8x16.StoreArray", simdStore())
	addWasmSIMD("simd/archsimd", "LoadUint16x8Array", simdLoad())
	addWasmSIMD("simd/archsimd", "BroadcastUint16x8", simdBroadcast(ssa.OpBroadcastInt16x8))
	addWasmSIMD("simd/archsimd", "Uint16x8.StoreArray", simdStore())
	addWasmSIMD("simd/archsimd", "LoadUint32x4Array", simdLoad())
	addWasmSIMD("simd/archsimd", "BroadcastUint32x4", simdBroadcast(ssa.OpBroadcastInt32x4))
	addWasmSIMD("simd/archsimd", "Uint32x4.StoreArray", simdStore())
	addWasmSIMD("simd/archsimd", "LoadUint64x2Array", simdLoad())
	addWasmSIMD("simd/archsimd", "BroadcastUint64x2", simdBroadcast(ssa.OpBroadcastInt64x2))
	addWasmSIMD("simd/archsimd", "Uint64x2.StoreArray", simdStore())
	addWasmSIMD("simd/archsimd", "LoadFloat32x4Array", simdLoad())
	addWasmSIMD("simd/archsimd", "BroadcastFloat32x4", simdBroadcast(ssa.OpBroadcastFloat32x4))
	addWasmSIMD("simd/archsimd", "Float32x4.StoreArray", simdStore())
	addWasmSIMD("simd/archsimd", "LoadFloat64x2Array", simdLoad())
	addWasmSIMD("simd/archsimd", "BroadcastFloat64x2", simdBroadcast(ssa.OpBroadcastFloat64x2))
	addWasmSIMD("simd/archsimd", "Float64x2.StoreArray", simdStore())
	addWasmSIMD("simd/archsimd", "Int8x16.AsInt16x8", makeAsOp())
	addWasmSIMD("simd/archsimd", "Int8x16.AsInt32x4", makeAsOp())
	addWasmSIMD("simd/archsimd", "Int8x16.AsInt64x2", makeAsOp())
	addWasmSIMD("simd/archsimd", "Int8x16.AsUint8x16", makeAsOp())
	addWasmSIMD("simd/archsimd", "Int8x16.AsUint16x8", makeAsOp())
	addWasmSIMD("simd/archsimd", "Int8x16.AsUint32x4", makeAsOp())
	addWasmSIMD("simd/archsimd", "Int8x16.AsUint64x2", makeAsOp())
	addWasmSIMD("simd/archsimd", "Int8x16.AsFloat32x4", makeAsOp())
	addWasmSIMD("simd/archsimd", "Int8x16.AsFloat64x2", makeAsOp())
	addWasmSIMD("simd/archsimd", "Int16x8.AsInt8x16", makeAsOp())
	addWasmSIMD("simd/archsimd", "Int16x8.AsInt32x4", makeAsOp())
	addWasmSIMD("simd/archsimd", "Int16x8.AsInt64x2", makeAsOp())
	addWasmSIMD("simd/archsimd", "Int16x8.AsUint8x16", makeAsOp())
	addWasmSIMD("simd/archsimd", "Int16x8.AsUint16x8", makeAsOp())
	addWasmSIMD("simd/archsimd", "Int16x8.AsUint32x4", makeAsOp())
	addWasmSIMD("simd/archsimd", "Int16x8.AsUint64x2", makeAsOp())
	addWasmSIMD("simd/archsimd", "Int16x8.AsFloat32x4", makeAsOp())
	addWasmSIMD("simd/archsimd", "Int16x8.AsFloat64x2", makeAsOp())
	addWasmSIMD("simd/archsimd", "Int32x4.AsInt8x16", makeAsOp())
	addWasmSIMD("simd/archsimd", "Int32x4.AsInt16x8", makeAsOp())
	addWasmSIMD("simd/archsimd", "Int32x4.AsInt64x2", makeAsOp())
	addWasmSIMD("simd/archsimd", "Int32x4.AsUint8x16", makeAsOp())
	addWasmSIMD("simd/archsimd", "Int32x4.AsUint16x8", makeAsOp())
	addWasmSIMD("simd/archsimd", "Int32x4.AsUint32x4", makeAsOp())
	addWasmSIMD("simd/archsimd", "Int32x4.AsUint64x2", makeAsOp())
	addWasmSIMD("simd/archsimd", "Int32x4.AsFloat32x4", makeAsOp())
	addWasmSIMD("simd/archsimd", "Int32x4.AsFloat64x2", makeAsOp())
	addWasmSIMD("simd/archsimd", "Int64x2.AsInt8x16", makeAsOp())
	addWasmSIMD("simd/archsimd", "Int64x2.AsInt16x8", makeAsOp())
	addWasmSIMD("simd/archsimd", "Int64x2.AsInt32x4", makeAsOp())
	addWasmSIMD("simd/archsimd", "Int64x2.AsUint8x16", makeAsOp())
	addWasmSIMD("simd/archsimd", "Int64x2.AsUint16x8", makeAsOp())
	addWasmSIMD("simd/archsimd", "Int64x2.AsUint32x4", makeAsOp())
	addWasmSIMD("simd/archsimd", "Int64x2.AsUint64x2", makeAsOp())
	addWasmSIMD("simd/archsimd", "Int64x2.AsFloat32x4", makeAsOp())
	addWasmSIMD("simd/archsimd", "Int64x2.AsFloat64x2", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint8x16.AsInt8x16", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint8x16.AsInt16x8", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint8x16.AsInt32x4", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint8x16.AsInt64x2", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint8x16.AsUint16x8", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint8x16.AsUint32x4", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint8x16.AsUint64x2", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint8x16.AsFloat32x4", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint8x16.AsFloat64x2", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint16x8.AsInt8x16", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint16x8.AsInt16x8", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint16x8.AsInt32x4", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint16x8.AsInt64x2", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint16x8.AsUint8x16", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint16x8.AsUint32x4", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint16x8.AsUint64x2", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint16x8.AsFloat32x4", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint16x8.AsFloat64x2", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint32x4.AsInt8x16", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint32x4.AsInt16x8", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint32x4.AsInt32x4", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint32x4.AsInt64x2", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint32x4.AsUint8x16", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint32x4.AsUint16x8", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint32x4.AsUint64x2", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint32x4.AsFloat32x4", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint32x4.AsFloat64x2", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint64x2.AsInt8x16", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint64x2.AsInt16x8", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint64x2.AsInt32x4", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint64x2.AsInt64x2", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint64x2.AsUint8x16", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint64x2.AsUint16x8", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint64x2.AsUint32x4", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint64x2.AsFloat32x4", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint64x2.AsFloat64x2", makeAsOp())
	addWasmSIMD("simd/archsimd", "Float32x4.AsInt8x16", makeAsOp())
	addWasmSIMD("simd/archsimd", "Float32x4.AsInt16x8", makeAsOp())
	addWasmSIMD("simd/archsimd", "Float32x4.AsInt32x4", makeAsOp())
	addWasmSIMD("simd/archsimd", "Float32x4.AsInt64x2", makeAsOp())
	addWasmSIMD("simd/archsimd", "Float32x4.AsUint8x16", makeAsOp())
	addWasmSIMD("simd/archsimd", "Float32x4.AsUint16x8", makeAsOp())
	addWasmSIMD("simd/archsimd", "Float32x4.AsUint32x4", makeAsOp())
	addWasmSIMD("simd/archsimd", "Float32x4.AsUint64x2", makeAsOp())
	addWasmSIMD("simd/archsimd", "Float32x4.AsFloat64x2", makeAsOp())
	addWasmSIMD("simd/archsimd", "Float64x2.AsInt8x16", makeAsOp())
	addWasmSIMD("simd/archsimd", "Float64x2.AsInt16x8", makeAsOp())
	addWasmSIMD("simd/archsimd", "Float64x2.AsInt32x4", makeAsOp())
	addWasmSIMD("simd/archsimd", "Float64x2.AsInt64x2", makeAsOp())
	addWasmSIMD("simd/archsimd", "Float64x2.AsUint8x16", makeAsOp())
	addWasmSIMD("simd/archsimd", "Float64x2.AsUint16x8", makeAsOp())
	addWasmSIMD("simd/archsimd", "Float64x2.AsUint32x4", makeAsOp())
	addWasmSIMD("simd/archsimd", "Float64x2.AsUint64x2", makeAsOp())
	addWasmSIMD("simd/archsimd", "Float64x2.AsFloat32x4", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint32x4.BitsToFloat32", makeAsOp())
	addWasmSIMD("simd/archsimd", "Float32x4.ToBits", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint64x2.BitsToFloat64", makeAsOp())
	addWasmSIMD("simd/archsimd", "Float64x2.ToBits", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint8x16.BitsToInt8", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint8x16.ConvertToInt8", makeAsOp())
	addWasmSIMD("simd/archsimd", "Int8x16.ConvertToUint8", makeAsOp())
	addWasmSIMD("simd/archsimd", "Int8x16.ToBits", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint16x8.BitsToInt16", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint16x8.ConvertToInt16", makeAsOp())
	addWasmSIMD("simd/archsimd", "Int16x8.ConvertToUint16", makeAsOp())
	addWasmSIMD("simd/archsimd", "Int16x8.ToBits", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint32x4.BitsToInt32", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint32x4.ConvertToInt32", makeAsOp())
	addWasmSIMD("simd/archsimd", "Int32x4.ConvertToUint32", makeAsOp())
	addWasmSIMD("simd/archsimd", "Int32x4.ToBits", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint64x2.BitsToInt64", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint64x2.ConvertToInt64", makeAsOp())
	addWasmSIMD("simd/archsimd", "Int64x2.ConvertToUint64", makeAsOp())
	addWasmSIMD("simd/archsimd", "Int64x2.ToBits", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint8x16.ReshapeToUint16s", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint8x16.ReshapeToUint32s", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint8x16.ReshapeToUint64s", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint16x8.ReshapeToUint8s", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint16x8.ReshapeToUint32s", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint16x8.ReshapeToUint64s", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint32x4.ReshapeToUint8s", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint32x4.ReshapeToUint16s", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint32x4.ReshapeToUint64s", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint64x2.ReshapeToUint8s", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint64x2.ReshapeToUint16s", makeAsOp())
	addWasmSIMD("simd/archsimd", "Uint64x2.ReshapeToUint32s", makeAsOp())
}
