So our next presentation will be from Lottick-Grabinski.
We have had a number of presentations on the various bits of hardware and the missing
component is always the open PDK.
We are going to hear now about how to fill in these gaps with the open PDK initiative.
So please give a warm welcome to Lottick.
Thank you very much for your introduction.
I am really happy to join the forum and having you recognizing the importance of our open PDK
initiative.
I am standing here for IHP, IHP's R&D institution in Germany in Frankfurt on
other, so it's a Polish German border, it's other Frankfurt, and they are very
fair to join open PDK initiative.
I will present the status that tools we are establishing for mainly analog RF design and at
very end our vision of federal development following recently published Rautma.
And what the Grabinski is my private direct email address, I am also managing Mosek
K Association, which all organized serious of compact modeling, spy simulation workshop
and very bottom, it's my direct email address at IHP when I am consulting for open PDK
initiative supporting IHP team.
This is outline and I will start with motivation.
As you see this forum that's depleted and the issue or question about building
talents and skills for our engineering domain, it's quite critical.
I'm referring to quite old presentation by Joe DeBoc, the VP of IHMek.
He was addressing this issue on different forums, including public hearing of European
chip arcs in Strasbourg.
It took European Commission about two years to come to this numbers.
Our room is depleted, it's not only this room in our microchronics engineering domain,
but as you see everything from designs, tests, software development in our semiconductor
microchronics domain lacks huge number of technician engineers researchers that different
reason for this, but we believe that open PDK in each out of its solution, it will help us
to attract younger generation students, young engineers, researchers to our domain
to support all what we are doing. We are not very first to face this issue.
In India project a faulty project and each of them is a project
are running for a couple of years. They are to my understanding what I remember, they were very
first to use complete open source design flow to introduce maybe not-tingering engineers,
but that young students and engineering to a mallectronic. They started with
a simple second design using discreet components, they were simulating with engineers,
engineers, what was introduced earlier and doing PCB boards with Kikat and what is important
to highlight, they are not just introducing the tools, but they have huge library, they call this
spoken tutorials where they address different topics of circuit design, modeling simulation,
PCB design, moreover they translated to local languages also to other languages including
European, I was surprised to see huge library of spoken tutorial in Portuguese. So just visit
website and you will find really a lot of resources even for beginner to start joining our activities.
Our friends with Google support in United States, they joined or they were very
first to open pdk's and they managed to convince sky water and global funderate that two
I see manufacturers in the United States offering not only open pdk, but they built complete
open source design flow. China, they do not sleep, they have initiative one student one
chip and they claim having something like 10,000 student doing designs, I wish I could have a
fraction of my electronic student designing chips in Europe. The same applies to Japan,
they follow concept of Google and Fabulous, but they are talking to domestic funders to join in
IHP offers unique process it's bipolar with silicon germanium devices operating up to 450
gigahertz on silicon germanium silicon germanium semiconductors this is unique it's about half a
terahertz silicon devices there is a complete set of devices available for
analog RF design for all who are within digital it's based on standard CMOS process
little bit telegacy 130 but it's perfect for digital huge digital blocks prototyping.
All what we are offering it's not open pdk it's not only design flow we have built but we also
offering free multi-project waveforms so if you design your circuit in this flow you can submit
this year we have four subsequent type out your submit your design will be validated
sent for manufacturing at very end you will receive hopefully working piece of silicon chip for testing
scan the QR code which points you to all information about submission
precision so I will keep this slide for a while
this is this is I like really high level abstract view on all what is available in pdk
you learn about different components first column it's probably it does not turn is it
part of open pdk but then passive components individual semiconductor devices
digital cells a part of schematic view behind each device passive or active there is
other representation for passive components we need 3D modeling so there is input to run
electromagnetic simulation and going from schematic to real integrated spiral inductor in your chip
the same applies to semiconductor devices most fed by polar or digital blocks or digital cells
which has a very low pure very low digital representation and then having a layout you are
submitting your chip for manufacturing this is not a part of open pdk but for all who are working
at the device level trying to understand the physics I would recommend to go through
ticard tools and we have huge selection this is just for example of 2D 3D modeling simulation
tools cider is fully integrated with ngspice so virtually you can do numeric
semiconductor device modeling and simulation without leaving ngspice and then build this
numeric representation simulated device in your sub-circuit you can imagine having numeric
alert presentation of your MOSFET device spice model you can build sub-circuit and simulate
complete sub-circuit with ngspice digital flow it's well established we are using open route
and to explain this slide probably I would need yet another presentation we are focusing on
RF design this is what we brought together we have quacks and xm for schematic entry with ngspice
and zi for transistor level simulation k layout on magic for layout gds to design the tools
supporting design rule check physical validation this is like last week extension we have also
parasitic extraction tool supporting k layout I was referring to numeric simulation we need to
numeric assimilation for passive components interconnex transmission line integrated
antenna spiral inductors which are part so we have two tools which are open source
open ems and we have also elmer for these tasks always well defined and you can find even
well prepared set of dockers with all the tools which I'm listing here you already know
quacks it was presented a couple of times at first them also within this room I'm glad to see
for the developers joining us here on each slide you have a reference to page where
tool is available for download I already talked about numeric assimilation we need this to get
spice or representation of spiral inductors it could be set of esparometers or lumped model
passive component sub-circuit to represent quite complex in fact to the structure of spiral
inductor which is part of an analog design compact model of very critical for
open pdk and in particle spice libraries they are core of the pdk the quality of pdk
quality of your design depends on the the model how it was extracted implemented
having all statistical core of the models short distance matching for analog simulation
the references explaining very log a code it's a game topic for yet another lecture this
keyword was coming in and despite presentation no cover presentation we have outstanding very fast
robots very log a compiler to bring new models to our pdk compact model verification validation
is critical so I'm glad to my application to develop test precision for model
validation was recognized and is supported by an neural net
buff was briefly introduced I will skip this slide again there are references and
Felix was talking about alternative tool which would allow very log amst complete model
compilation kikat as we here in this room it's important tool because after designing
geochip you have a piece of silicon eventually package and then you have to create the
test board to validate and it's a former area presentation by holder he was talking about
engine spice which runs in the background of kikat which allows you to validate your
seconded boarder ever all what we do at IC level with quarks or xhem so engine spice or size
are really core simulation tools for all what we are doing testing it's important
I was presenting this 2018 it did not draw attention but others they went even feather
and brought unique platform to introduce student to simo's second single transistor
characterization measurement and simulation and there is this Mobius chip which we recommended for
open pdk and eventually will be manufactured in the one of upcoming runs this are digital designs
each individual design it's multi million even multi core risk farf implementation which has been
submitted for open pdk multi project waferan and they are manufactured at iHP
there are a lot of publications where you can learn about design procedures starting from high
level abstract like cut definition going down to synthesis of your chip and creating integrated
circuits analog design it's not fully automatic they are we have a partners which are
joining our open pdk initiative and coming with the analog design automation tools similar to
open route but for analog RF application. Mosaic it's one of possible frameworks to work on IC design
our partners at sub one university they have the color coriolis platform
targeting fully automated design from second description sizing the parametric
structure and eventually generating a working chip this is the project from united state they
try to use machine learning AI to do automatic fully automatic layout generation this is the
public project but unfortunately layer of machine learning models it's proprietary this was
ran we together with Intel and as you can imagine Intel keeps all the models for themselves but we
have framework to start with there is a lot of activities around it's a little bit chaotic so i'm
glad that go IT project and fossil foundation free open source silicon foundation they
define open source ideate route mark for europe this document has been submitted to brassel it's
an evaluation and eventually would lead to new european level R&D project to cover this free domain
open source analogs mix mode design productivity interoperability verification and third one digital
system on chip this is at the digital level including open source tools so all what we are doing
in open source tools i hope we'll be recognized and final support at european level
all this teamwork this top list it probably does not include all who contributed to
couple of points i was addressing R&D results is our team manager coordinating all in open
open pdk in shot of a DHP serving under a lot of industrial experience and bringing this to
open pdk domain we have partners at ith in story university technical university in linked
i was referring to bomb by and they are also entering open pdk and we'll set up the tools
to support our processes all it's open source it's not free so we are happy it's free to download
and use but it's not free to develop so we we're happy that this was recognized in germany by local
funding agency i i i'm glad that it was very first to support this activities and funding
organization including micro electronics research funding organization and federal means of research
and education in germany this contributors to open source route we have our partners from iHP
contributing and their group of volunteers are edited jointly this proposal and again this is
at evaluation in Brazil so if you want to learn more you are more than welcome to join us at
serious of open pdk workshop session and different events around the world i hope to be
transmitting you again and continue our discussion oh
questions
thank you for this beautiful presentation i have a question where can i find information for using
iHP pdk with very low a i fan i from noting on the github so very low a models for semiconductor devices
we are using psp MOSFET model in very low which is compile and it's part of
angispice simulator and the same applies to edge bt models by polar transistor models which is
vbic it was also compile it's part of angispice open pdk provides libraries and in libraries you
have all parameters for these two transistors MOSFET and bipolar which you can design circuit and
then eventually simulate with angispice we do not have very low a models for other components
digital cells are represented as cell view with spice level net least for all digital blocks
we do not have very low very low digital models for digital cells
yes there should be should be link
follow this link this is information about preparing here design for
manufacturing with this for subsequent tape outs and if you follow there is
installation information how to download open pdk from github how to install you build the
three of libraries directory accessing the cells and they are a commendation how to configure it
basic tools coax for schematic entry angispice or size for circuit level or transistor
level simulation k layout all the tools validation verification tools for k layout so we have this
flow it's not smooth transition from one step to another but it's already well established
other tools for automatic design automatization of analog RFC I assist it's kind of work in
products progress and we have this I wanted to free different platform which could automatize digital
flow in case of digital design we are recommending open line and you start with your high level
very lock CPU you can get risk five and then go through automatic synthesis and with
generates your GDS 2 file targeted for iHP by CMOS process yes please
okay I have lots more questions you mentioned that it's free to download but not free to
manufacture so I don't know it's free to manufacture I also feel that this last QR code
with offering free multi wafer multi project wafer runs so if you are student if you are
academic partners you can submit your design will be verified validated if you qualify you will get
free silica we cannot sell chip you are getting free loan of your chip there's simply
legal procedure and in fact I HP owns your chip and you are getting this on the loan but
then period is undefined so you you take your time to measure validate your chip now it's a
it speeds federal R&D institution and cannot give something for free so we are offering the chips
you design as loan for you to test you can share with your partners other who contribute to the
but in the end if you want to go to the like full scale production is that also possible
yes I HP have subsidiary which is called iHP solutions and they are coordinating low
volume production and then of course we are coming to the business so it's other aspect more
commercial aspect on the iC design and the links for all of this will be in your presentation
yes I already have a blog so if you check out for them web page of our
Deferum my slides are online each slides has corresponding link to all what I was present
one last question maybe final one the rest in your PEDK you provide sales to the functions
but if I design myself full custom sell and I want to integrate it in in a chip which is approved
for your wafer run is that possible or yeah there are no risks that you can see this part like
transistor or sell design flow independent so you will create your schematic representation
spice net least and eventually layout which you have to verify do design roll check LBS parasitic
extraction so you will be responsible for your new block or sell you are designing and then we
have all tools to validate verify your new block but there is no risks yes there are any more questions
yes I will be available and we will be happy to talk to you thank you very much very welcome thank you