A number of weeks or months, depending on how much data you have in order to get a model.
But really, this will not get you rich, this will give you a big electricity bill, a big
hardware bill.
But what will get you rich is the actual inference when people are querying that a
base or doing some searches for something.
So that's the point of the first line, trading is interesting, but inference is for
her, and that's where you want to be effective in those accelerators.
But of course, those accelerators go in big enterprise, data centers, and of course,
you will waste lots of electricity on them, it can't stop.
And of course, you need to have large engineering team.
But, you know, it's totally possible to get into that business right now with risk five.
Because when you look at this accelerator, it is a very simple design.
You just take a basic processing element.
You copy it a few times, a few dozen times, you know, and the thing is, if you have
the proper IO's, then you have a chip perfectly, you know, capable to do that kind
of inference at scale, you know, in a big enterprise data center.
So maybe you start smiling, you grow, and, well, if you find the niche, other than boring
ads, then maybe AI would be useful.
So that's one way where, essentially, you could use risk five as this building block.
Because of course, the AI specific sauce would be up to you, but anything which is
generic computing that chip, you know, can be built using open source risk five designs.
And that's the way to do it, because you don't want to reinvent the wheel with your own
custom architecture for everything.
Well, maybe this would be fun, but this would not be fast to market or profitable.
Then, of course, the AI at the edge is a big topic.
We have plenty of devices, all of you replace with built in AI, built in intelligence.
And, well, a good example of that is this little AI chip by a sort of accelerer.
So in that case, it's really a low power design, so you could run this in the field on
battery powered, consumes just a few watts, okay, and probably if you would optimize it
more, maybe it would go down up to a few million watts.
And, well, that's great for a wide range of embedded, deeply embedded applications.
In that case, the hardware is fairly small, so it could fit on a small M2 form factor
board, okay, so a very small chip with the supporting components.
And really, when you look at this, this is yet another very simple design.
You have common building blocks with a risk of five controllers, and of course, security
on the chip built in, because, well, if you are deploying this in the field, you need
secure boot, you need accelerances that someone would rip off the device from the wall,
let's say, wouldn't be able to access the data and be rich instead of you.
Well, no, they are privacy implications and other like that, other things like that, of course.
So really, the fact that the security is built in, in the case of this particular design
is really fundamental, because you are deploying in the field, and so you need, you want
to ensure that the data is private, and of course, that it stays really uncompromised.
And, not your way to do this is to deal with, maybe, commercial vendors.
So, for example, and desk technology, we'll known a risk-five vendor, they've got a number
of risk-five cores, of course, but then they will happily license you their AI building
blocks as well.
So this is what industry to there, so you have a diagram for the type of core or chip
that they would sell you.
And of course, you know, they have an extensive software stack going well that, so they
will provide you optimised compilers, real-time operating system, even an IDE if you want
to use that, and what's wrong with them, anyway.
All of that to say is you've got everything in the box to get you started more quickly,
but in this case, their own business was only possible because risk-five was around providing
this very stable foundation, and then they were able to build something that's really an
interesting licensing place, so, you know, join the fund, that's yet another possibility
for a startup if you are so inclined.
And then, of course, there's plenty of AI in your pocket, right, and most phones today
are able to do AI, but even for non-AI functions, have plenty of risk-five cores built
in for power management, or screen management in the camera, all over the place, even
fruity smartphones, so to speak, if you like, Apple's, you know, we'll have built-in
risk-five controllers in the main SOC to do various things, right, and of course, they
won't, they won't share that, those are not open source design.
But all of that to say is that there are plenty of examples of, you know, using risk-five
technology and build that into a more complex system to really deliver specialized things.
So, if you build such a small AI accelerator, let's say that you want to embed into
a non-based device, or even it's a device, you can do it, and once again, that's a business
opportunity for you, and that's a business opportunity because, essentially, a risk-five
is around and gives you a relatively free open building block to start with.
But of course, well, that's a thing, risk-five is just the instruction set, and there
are plenty of risk-five people that came on this stage earlier that will tell you about
their marvelous boards and multiple scores and everything like that, but all of those
things are proprietary, right, so you wouldn't necessarily have the source for that.
So, what we do at Open Outwear Foundation is really to work on open source cores and even
open source microcontrollers in one case, and provide those building blocks to the community,
but at the same time, the focus is on industrial grades, so we do verification on those
things, and I'm not the chip designer, Jeremy is, so we can tell you more about this aspect
of things.
Now, of course, you know, saying that we have risk-five cores could be anything, but really,
in our case, the focus is really on smaller cores that go once again in a variety of embedded
applications.
Starting with CV2, which is roughly equivalent to the ARM Cortex M0, and then in the
middle, the most popular family, let's say, so the CV4 family, where essentially we
have equivalent for M4s or M2T3s on the arm side, and in this case, they are several variants
with specific variations or specific feature sets, different from each other, but all of
those are on GitHub in open source, and you can play with them and modify them, run them
on FPGA, or even go get a chip made.
And finally, CV6, CV6, in this case, runs Linux, so it's of course, a bigger and more powerful,
and equivalent to ARM Cortex M0 or A55, in that case, so plenty of potential applications
to all of those things, and of course, this is just what we have on the roadmap.
We have, you know, longer-term plans for more powerful chips, eventually, in a can of
stuff, so that's what you see, the CV8, for example, would be more powerful than all of
those chips.
So, once again, this, in the case of the open other Foundation, is a community driven
set of projects, which means that, well, if you find this interesting and join, then
we could go even smaller than the CV2, or even bigger than what CV8 is.
This is all about, you know, bringing new members, bringing new ideas, and going where
you want to go as a community.
Once again, we are here, well, in my case, doing some part of the program management
there to support our members in whatever they want to do.
We don't necessarily dictate the technology direction.
And so, what, will you find at Open Outwear Foundation, in terms of actual deliverables?
Well, first, they are the course themselves.
They are under the soldered pad license, which is roughly equivalent to the Apache tools,
essentially.
You take it, you do whatever you want with it, just put a small, a smaller, recognition
in your readme somewhere that we've been around to provide you those building blocks.
So the course are defined in system catalog, so you will find the false source code
on GitHub.
And then there's all the supporting infrastructure around it, right?
So we have test benches, and of course, integration with most of the popular tools
that are used by actual chip designers, and not, so please don't ask me about this.
But once again, Dream is there, and it was more about those aspects than me.
And of course, our friend Flow, so if you're wondering, it was on the talk, well, it's
a really good thing for the first time.
So, I'm here, instead.
And so there's also a bunch of support software.
So we work upstream with the TLVM and GCC and Jeremy will provide more details about that,
but essentially we work upstream to ensure that our course are worth supported in those upstream
tools.
And then, of course, the open hardware foundation community worked on properly supported
VRTOS support, for, of course, the smaller course.
And we are starting to see an effort emerge around eclipse tradux as I will elaborate a bit
later.
And of course, there's plenty of documentation, and even board images for popular FPGA.
So once again, if you want to modify the course, test them, then if you have one of those
two FPGA's, well, the Nexus A7 will be appropriate for the CV-2 and 4, and the Genesis
2, of course, for the CV-6, it's more expensive, but more powerful.
You can actually boot Linux on that.
Now of course, software will make and break your chip.
And now it's Jeremy's time to shine, so I'll let us exchange a mic.
Thank you, Frederick.
Hopefully that's all good and clear.
My background's more on the software side, so I'm going to talk about this.
I'm co-chair of the technical work in group for open hardware foundation, which is
the technical oversight for all the technical work we do.
So within open hardware group, we break down into a small number of task groups to oversight
to see the different areas we work on.
We've got about five or six.
The open hardware software task group is chaired by my colleague, Paolo Savini, and it's
responsible for making sure that the software ecosystem we need is there around that chip.
The tool chains, that's absolutely essential, but operating system ports where they needed
any firmware that's needed for use the course and things like the SDK.
And this continues to evolve and the work with ThreadX is just one of the latest things
we're working on.
It's a collaborative effort, it's open source, but it does rely on the member companies
contributing to that effort.
It's not just someone in their spare time, so that's been done both by companies like
my and because I'm contributing, but also other companies actually funding us to contribute
even more because they don't have a software team but they can buy us to do it as well.
So that's how it's been done.
In terms of the compilers, we've got GCC and Lofium, the goal is to go up stream.
We don't want to maintain an out-of-tree compiler that is a whole world of pain of work
closed.
GCC 14.1 that came out last spring has five of the eight isher extensions for the CV-first
costs of processor.
There's three of them still in the review pipeline mostly because they're quite complex
and the amount of review effort that's needed.
KangelLVM18 has four of the extensions upstream that's running slightly behind.
That work is largely done by our colleagues at the programming languages and compiler team
of the Chinese Academy of Sciences.
So that team has been a huge contribution there.
They're all available to you, though,
because we do maintain an out-of-tree mirror
for the stuff that hasn't yet gone up soon.
So if you go to the open hardware groups,
GitHub, you will see that the source
for the remaining out-of-tree materials,
they're all the extensions are supported.
And if you like your compile-a-tree change pre-made,
you can download them from the Emboxon website.
So how far have we got with the tool chains?
Full assembler support, full built-in support,
where it makes sense for some functions,
it doesn't make sense to have built-in support.
So that's due to efficiently.
And for all but two of the extensions,
we also have automatic code generation.
We haven't yet got the code generation
for the Bitmin population,
because it is not standard Bitmin population.
And we haven't yet got code generation
for the SIMD instructions, but the rest of it's there.
Operating systems are the QEMU port.
That's a work in progress.
Do come and join in if you'd like to help with that.
There's free R-toss was done some time ago.
There's work on going with Zepha.
ThreadX, Frederick is much better qualified
to talk about and he'll talk more about that later.
There's no special Linux work,
because actually we don't need anything special on Linux.
It uses a standard Linux kernel,
but for Dora and Red Hat have been working
on then getting that all pulled together
at a system level.
So it all works on particularly CVACX.
And last, you have an ID.
Now this ID may not be, it is Ashley's risk free ID.
So it's a well-established industry ID based on,
in this case, eclipse, it'll actually run on other infrastructures,
as well.
But it's made available free for the open,
for the open hardware foundation,
and has the compilers, the debug, or everything built in.
It does everything you'd expect,
and you can just program in there.
You can plug into your FPGA board and it just works.
And well documented.
We have an MCU.
So in order to, we thought we'd make ourselves a reference MCU,
so not just the processor,
but some useful peripherals,
so you've got some networking connections.
You've got a timer, you've got buses to hook up to memory,
and so forth.
And that is the basis of the Core 5 Devkit,
which is a Devboard.
Now, I do have to say there's a slight catch here.
The first version of the chip we spun
had a metal layer error.
We do have a small number of working chips,
courtesy is a very clever laser use by our friends
at the University of Saskatchewan,
but there is a plan that this will be responding to you,
course, and then we'll have a working silicon.
So, and the idea of that is that we've got real
a sick type hardware that goes faster
and so forth, we can test things on.
Now, I want to just end, because this is a talk
about RIS 5 in AI, about an open source AI project,
that is RIS 5, it's Core 5 based,
and it is for the open.
You can go and download this from GitHub.
As a side interest, William Jones, who's my head of AI,
and I, Supervisor Group Design Project,
Southampton University, every autumn.
So, we have six, four to six students working on a project.
And we asked them a few years ago the question
of everyone's building these AI accelerators based on RIS 5,
which have the whole vector instruction set in,
and they take vast acres of silicon.
And that's not good for low-power applications,
and really do you need the whole RIS 5 vector extension
to accelerate AI.
So, we said, how small can you make it?
And they developed a derivative of CV-3040B,
extended with just eight RIS 5 vector instructions,
load and store, and one or two ads track multiplying and so forth.
So, a tiny extension, and the result of that was,
they got between a 5 and 7 fold speed up
on the tiny ML-Perv benchmark.
There is a video YouTube, they gave a talk
to the British computer society about this work.
It is the second most viewed video
from the British computer society open source group.
They're on YouTube, add all the sources on GitHub.
And so, I put that there, not because it's particularly
a software project, because I supervise it,
and I was doing the software talk, so I think you came
in the talk.
So, with that, I'm going to hand back to Frederick.
Thank you, all right.
So, why would you come play with us, right?
Because you want to get rich, you have ideas
for our NEI startup, so why work in open source with us?
Well, essentially, first, risk-5 is really changing
the game in terms of what you can do with AI,
because by using it as a building block,
you can focus on your accelerator and on your added value
on top, which means you get faster to market.
And from that perspective, once again,
it's one thing to have the I.C, but in our case,
we provide you in this real great, verified course
that you can leverage in your designs.
And, of course, since the license is very permissive,
you can use them as is, but you can improve on them, as well,
right?
And we hope that we get contributions back from that,
but nothing in the license forces you to do so, okay?
And really, the way that we operate is around three core values,
open, transparent, and meritocratic.
Open, being with everything in public, okay?
There are no hidden mailing lists or hidden room,
where you know the big guy stock, everything is done in the open, okay?
Transparent, of course, means that we have public road maps,
and I love that, you've seen the road map,
and of course, there's more detail information
on the open, other web foundation website.
You can join the matter most in order to interact
with the community.
There are plenty of ways that you can find us.
And even if you're not a member yet,
you can interact with us.
And meritocratic means that essentially,
the people with commit rights on the repositories
have to earn their way, right?
They need to prove that they have the skills
and that they've made contributions
before becoming core committees on those projects.
And a third big advantage of open-out web foundation
is that it really brings together industrial players
and academics.
And to give you an example, I was traveling two weeks ago
with Flow, we went to Montreal to put it
at Technique Montreal.
And we were visiting a professor there.
He's got a project, a research project called Polara.
And Polara was about making a physical chip out of the CVA6.
So I've seen that very particular chip, okay?
There's only an unfolding the word,
and that was quite, quite impressive as a moment,
because that was literally an open-source design
on a chip that I could plug into,
something and run the next on it.
So of course, they are challenges, okay?
And so to me, the technology needs to mature a little bit more,
but this is an impressive achievement,
and this is something that you could replicate yourself
if you're thinking about starting a business.
Of course, the cores are fully open.
There's nothing hidden in there.
And they are fully verified.
So challenge our IRTL, if you want.
But I mean, actual chip designers worked on this,
and we have, of course, the verification,
the validation reports to go with the technology.
And finally, well, if you love Europe, I do.
Then, well, open hardware foundation
is a part of the Eclipse Foundation.
The Eclipse Foundation is the largest open source
organization in Europe.
We have over 50% of our staff now in countries like France,
and Germany, Sweden, Romania, Spain, Italy.
So we're all available to place in Europe,
and so we are close to you.
We speak your language.
It's a piston toy.
I've known Poco is a Spaniard.
Anyway, it's a part of our service.
So I'll have that to say.
The Eclipse Foundation, if you care about Europe,
is the place to be.
So my call to action, learned about core five,
which is the name of our family, of course.
And of course, the Open Outwear Foundation,
visit the website.
We've got a YouTube channel with lots of interesting videos
that will get you acquainted with the technology, as well.
Try the code on GitHub.
The system very long is there, so if you're really a chip designer,
please have a look and let us know what you think.
And of course, engage.
So that particular link, the slides are already in the tools.
So when you click on it, you'll come to a section
of our website where you have all the ways to interact with us.
We'll find our references to the mailing lists,
the matter most instances and everything
that can get you connected into this.
And now the last slide, what we're trying to achieve there
by bringing Open Outwear Group into the Eclipse Foundation
as the Outwear Foundation is to build this comprehensive
and better risk-fifesteck, okay?
From the course, to the tool chains like the compilers
and we've seen with Jeremy,
we're taking this upstream work really seriously.
The real time operating systems
and in particular, Eclipse 3DX, Eclipse 3DX
is the only safety certified real time operating system,
which is also open source in the market.
So you can put it in cars.
You can put it in home appliances.
You can put it in medical devices today,
not two, three, four years away.
Like it would be the case with the affair,
but literally today we've got the certificates to prove it, okay?
So in this case, we are starting this effort
to port it to Core 5 and specifically the CV4 family
and eventually CV6 maybe.
Anyway, and also of course,
the Eclipse Foundation traditionally
was all about development tools.
So the traditional Eclipse IDE is still around,
but we've got also Eclipse TA, Eclipse TA
is like visuals to do called minus the Microsoft
and it's integrated with Open VSX,
which is a vendor neutral extension repository,
not controlled by anyone but owned by the Eclipse Foundation
on behalf of the Open source community.
So if you truly believe in a hardcore open source
approach and so to speak,
you've got all of the pieces there in the open.
And so this is not about just the traditional Eclipse IDE,
but really forward-looking technologies.
And of course, there's the rest of the Eclipse family.
So I'm also responsible for the Eclipse IoT working group.
So if you want an MQTT broker or something like that,
then you can go there on the problem.
And of course, we've got a full-blown software
to find vehicle working group.
So if you're thinking about doing AI
but around the automotive, then of course,
our SDB working group is a place to be.
So thank you very much.
It's been a pleasure to be with you today.
And now we've got some time for questions.
So.
So it seems the question microphone is dead.
OK, we'll repeat the questions then.
So please ask, I will repeat for the people online.
So the question here is the CV-2 and 4 families.
They are for embedded in CV-6 for more powerful things.
And yes, that's OK.
So CV-6 runs Linux.
So the question is why is the CV-4 or even CV-2 supporting
on the 32 bits?
That's a good question.
It's enough.
I think for the applications.
If a member came along and said I wanted to build a 64-bit embedded
class processor, sure, that would be fine.
The intention is the CV-6, which comes in 30 to 60
before the versions, is intended for application classes.
Of course, a typical microcontroller would be a few hundred
megahertz in clock frequency and maybe one megabyte of memory
or maybe five hundred, five hundred and twelve keys.
So in that case, even if the processor
core itself would be 64 bits, then it would be overkill.
And maybe it's a bit more power efficient to stay on 32 bits
for that kind of embedded application as well.
Yes?
Yes.
Is there a way to turn a better one in the next open neural network
or change format to the core specific instructions?
So the question here is, is it possible to convert
from the open network in X?
Oh, sorry.
Oh, yeah.
So the question is about ONNX, which is the open neural network
exchange format.
The, that has not been investment yet in the tool chain
to develop for that.
I recommend to the talk.
I'm going to be with William Jones tomorrow afternoon in the AI
on how to do that, which is an example.
Again, I think example project from Southampton University
is it happens on how we'll do that.
But yeah, that's generally a problem for anything
that's not an Nvidia chip.
So your question or comment is about the fact
that in terms of PCI express support, they are not,
let's say they are no good open source alternatives
currently that you could leverage.
Is that it?
The problem is not from this task, because me and my team
we kind of take on $1,000 of the complex IP
for PCI experts, so all can be too today.
OK, so it's very expensive to get access to the IP
for, you know, let's say a PCI express controller.
And so you're asking what you could do about that
in terms of implementing something.
Not sure if some members worked on such things.
I was saying more on the software side.
I mean, it's a general problem with peripheral hardware.
It's been forever going back to open calls days
that actually well-beating high performance peripherals
are really hard to design, and that hasn't
been a big enough community to do open source versions.
I'm sure if anyone would like to contribute a state
of the art high performance PCI, any sort of PCI express
interface we'd love to have it, and we'd
I'm sure welcome it as a part of the open hardware foundation.
But I don't know of an implementation.
Does anyone in the room know if an open
high performance implementation is open source?
Yeah, so the session like such, it has something that might help
towards that, that's good.
But it is PCI 2X, not PCI 3X, so PCI 2X, not PCI 3X, okay?
Okay?
Yeah, I have a question.
Oh, okay.
So are there any plans of aping out CES6?
You already taped out, I understand the 32 bit MCU, somehow the
like you explained the PCI 3X, the boat is not available,
maybe only available to members internally.
But taping out CES6 hasn't been pride, or is it still
let's say on the ideal side, and let's say never on an ASIC,
or GDS, it hasn't seen a found rate.
What is the plan going there?
So just in case the microphone wasn't loud enough for people online.
So the question is essentially if we are planning to tap out
have a physical chip of the CVA6, because in the case of the CVA4,
something something, in the context of the core 5 MCU we had,
those physical chips, I have a non-working board,
unfortunately with me in my back, I wish it would work.
But in the case of the core 5 MCU and the dev kit board that we've shown,
in fact, I think the PCB design for this is open as well, right?
Yeah, so everything, everything that we could make publicly available is.
But do we have the same type of plan for the CVA6 to my knowledge, no?
But I think the CVA4, I mean, that small,
it was easy, and it was done with the support of quick logic and silicon labs
to get it out the door, it's expensive to do that.
The CVA6, however, is being heavily used in a number of European research projects,
and I anticipate that those projects, so we've got any of the CVA6 people here,
there we haven't got them in the room, but I believe as some of those,
they will be doing some degree of taping out.
But I think you have to go and look at those specific projects last.
Of course, I mean, we could be creative eventually about that,
you know, and I'm just rambling off without the actual bus, you know,
flow being, you know, in Taiwan and all, you know,
if there's community demand from a number of, you know, companies that we're willing to
pull resources in order to make that happen, we would, of course, consider it, right?
But as Jeremy said, this is an expensive endeavor,
so if you want physical chips, you better join, and tell your friends to join,
etc. and then we get the money to make that happen,
because that's one of the things that I noticed in today's many presentations.
I'm coming to your question.
There's a lack of good, you know, validated boards or easily
of the obtainable boards in the market right now for people willing to work with this technology.
So maybe we can fix that as an open community.
So sir.
Well, we are members of the RISFF Foundation.
We are on a number of their committees.
Maybe Jeremy knows which one.
Individual members, most members of Open Hub,
with my company, for example, I'm members of RISFF International,
and will be on committees there.
And there is engagement with chief executive,
level to chief executive, of the CTA,
trying to coordinate what we do.
And indeed with the RISF Foundation and other organizations,
it's not just RISF.
So we're one big appeal, open family, so to speak.
Yes.
That, I have no idea.
So the question is which PDK flow and I don't have an idea.
At this point, it comes clear, I'm not really a hard-wrenching there.
So the answer is I don't know, but it's a question we can take away and get the answer back.
There is people who have looked at that and the open hardware,
the print open source silicon foundation has regularly had key
stock projects to try and actually get this fully open.
The actual defined flows, though, are not open source.
They use synopsis UVM flow, I think.
So I'd love it, I'd love it if someone wants to pick that up,
and you can do it.