Okay, so the first speaker is EML from canonical and he'll be talking about risk
five hardware where we're at.
Welcome.
Thank you.
All right, yeah.
So I thought I'll start out the day by not so technical talk, but just like introducing
you to what hardware can we actually buy right now.
As I began set, I'm EML.
I'm a kernel engineer at canonical and I do the risk five kernels for Ubuntu.
So in order to understand this landscape of what hardware we can buy, I think it's important
to understand three constants.
The first is the core.
That's the actual logic that looks at the risk five instructions and sort of run
the program.
That's the suck.
That's the chip you need.
It's a physical thing.
You know, the scent that can compute.
And then the board is the green plate that you also need.
So let me just go through this and talk a bit about what I mean.
So the core usually written in a very lock.
It's kind of like programming, but also not.
It's a design, not a program.
You can see example of a bit of a very lock at the side there.
Yeah, so that's a piece of logic that runs your code.
And this is where you can do like faster slower designs or smaller bigger designs
depending on how you should stuff.
Then you need the actual chip.
These days we put more than just the core on the chip.
So we call it a system on the chip because you see the yellow boxes up there.
That's the actual course.
But at the side there's lots of all the stuff.
Peripherals like you'd need for Ethernet, USB, MNC.
You also need like clock trees and a memory controller so you can have external RAM.
You need lots of stuff inside of the stock.
And all of those peripherals you can usually buy from different vendors so you can piece together your own suck.
Kind of like in the old days you would buy a network car and a graphics car and an ID controller.
Just on a very small scale.
Lastly you need the actual board because like the stock can't run anything on itself.
It needs like crystals for timekeeping.
It needs different power levels.
It needs something called decoupling.
It needs the external RAM.
It needs files to translate between the digital world world inside the chip and what you actually send on the wire.
It needs connectors so you can plug in your USB stick into something.
And they can be small like one at the top.
That's like a Raspberry Pi size.
Or they can be big and put into like a cabinet so you have something that looks like a real computer.
But I think it's important to understand all these three things in the when I go forward.
Because I'll just go and here this part I have two minutes light so try to make this quickly.
So in the beginning there was sci-fi.
And that's basically started by professors and PhD students from Berkeley where the risk five instruction set originates.
And one thing that's important to understand about them is that they're not in the business of selling chips or bots.
So what they really want to sell is just the design.
The core I was talking about but also other stuff.
So in 2018 I think it was announced here at first.
They made the list on least board and as you can see they designed the core.
They produced the chip and they also produced the board.
And the reason they did that even though what they really want to sell is just the top part they call.
This is like a tech demo to show the world this works and it does work.
I mean I have one at home and it runs.
That's so fast for the ones.
It's also like a very simple chip.
It only has like an even that controller that's fast everything else is super simple.
Anyway, they actually did sell this core to for example micro chip.
I'm sure it's a bit company you might know it.
And here you can see it gets a little more interesting.
You see the sci-fi design the core sold it's a micro chip who produced the chip.
And then they also created their own isolated kit.
But a lot of other companies made boards with this.
And I mean it's a nice chip.
If what it is it's an FPGA with some display cores on the side.
And it's good for that but you probably wouldn't buy it to just for the cores.
Because they're like the first generation of sci-fi cores and they're fast.
But they work.
They can run. In fact, it's a support a quite well upstream in Linux.
And that's also why you see bigger boarding in 2023.
A bigger board made the bigger we fire with this chip.
But wrong way.
Okay, two years later there's like the second generation of tech demo from sci-fi.
And as you see again they made on three parts.
They suck in the board. And of course a new core.
They wanted to demo.
But something interesting happened here.
There's a Chinese company.
Stuff five who also produced a their own chip.
But with the same core.
This was like a test chip for the upcoming product.
The next chip.
And it's the slices of a little misleading.
Because actually the starlight board over there was first.
There was like 800 out of them.
I was lucky to get one of them.
And then unfortunately a big board and see two people.
And stuff I broke up.
So stuff I produced is later their own board.
There's like 3,000 of those.
Yes.
Fast.
So what stuff?
They didn't come out of nothing.
Since I was actually started as sci-fi sort of Chinese branch.
But they're now independent and designing their own course.
But to give them credit,
the Chinese vendor that actually has the most upstream present.
Which I think is nice.
Because a lot of other Chinese vendors are good actually.
But they're not the only Chinese player.
There's a, a little Baba have a like a design team.
And they did something quite interesting.
They not only did they produce course like sci-fi.
They also put them out on GitHub.
They're the shanty course.
I don't know if I should call them home source.
But at least you can go go look at some of the very locked on them.
And then it got really interesting.
Because then you can see.
Now all winner took those small fancy course.
Put them on a chip.
And then lots of other Chinese companies produce course with them.
That's why they dot something.
There's plenty of other things.
These are some of the examples that are quite well supported.
Obviously.
And another important that I want to mention.
Just to show that it's not only tea head and sci-fi course.
It was there.
Was this.
There's another.
It's a Taiwanese company and it's who.
They actually sell a lot of like mic control of course.
But they also do logic course.
They can run Linux.
Sold them to run.
They usually do like automotive arm sucks.
But they also did this part.
And I was really hoping for this.
But unfortunately it has a box.
So it can run.
You need to compile the whole user space to work around this box.
Which is a bummer.
Because that means we can't run a bunch on this.
Like the other box you saw.
We have a bunch of images for them.
We can't have a one for this one because it has a box.
But I mean it is supported upstream in Linux.
Which is nice.
One way again.
Then.
Here we go.
2022.
Finally stuff.
I released the real chip.
Not just the test chip.
And this is like.
This is what I would recommend.
If you just want something easy.
Something that works.
We have plenty of images.
Those for like different digitals.
Wouldn't to include it.
Get the vision five or the mass board from the five.
But you can see there are lots of other boards up there.
I think actually now the start 64.
It also has a device tree upstream.
So you can run upstream.
Kind of some of these boards.
And it's super easy.
Good images for all the research.
If you want.
Basically.
And.
But I mean just.
Expect the recipe.
Buy three.
It's sweet.
It's not like they're super fast.
But.
For most of them you can actually attach them in your need drive.
So they have proper storage.
Which is nice.
Later.
23.
There's.
Now you can see actually.
He had they produced their own suck with.
A little a little faster call.
Uh.
My impression is that they needed this suck to do android porting.
But.
In any case, they sold it to a lot of other.
Um.
Companies that makes boards for this.
And.
There's a little scale way.
Uh.
Logo down here.
And that's because.
Uh.
I don't know if you've seen scale ways of French hosting provider.
You can buy virtual.
Which five machines from them or actually real hardware.
And the real hardware is this chip.
Um.
I would not be surprised if they just bought a bunch of those.
Uh.
Did you buy a cluster for a that you see just above their logo.
But I don't know.
It's.
It's this chip.
At least.
And then.
Ha ha.
They're planning you might've seen this.
It's the best.
So it has 64 goes and that's again, the.
The T hit course.
Uh.
And a lot of memory.
And, uh.
Uh.
I think I saw the PCI driver getting up to in town.
So maybe soon you can run upstream on it and actually use it.
But this is still your best bet if you just want to.
Compile GCC or the kernel.
Basically it's well.
It's.
Probably get it done fast.
But.
Uh.
see later those first generation of T-head course, they are first generation.
But here is the second generation, where they actually have the real, ratified version of
vectors.
So in 2013, it came also this little boat that was popular for a short while when this
was the only boat you can get with the vector in hardware.
So you can actually test your crypto, decoding, audio, video decoding with the vector extensions.
But it's very small and it doesn't have a lot of RAM.
So luckily later came this boat.
To me unknown, Chinese company called SpaceMit, with apparently their own core.
And they produce two different versions of the chip, I think it's the same, just one
of them, can be run a bit faster.
And then again, lots of other companies did possible then.
And later you'll hear from youening, from T computing, who also did like the second
laptop with the chip.
This core, I've been told that they started with the T-head course and then sort of developed
from that.
But it's not something I know for certain.
Yeah, this is also the air where we got our first sort of hardware bug with the logo.
And by now I hope you will be able to see that when it says down here, breaks in secret
of T-head with 5 CPU.
What they mean is that it's a bug in those T-head course.
So now you lot to be able to understand why this affects a chip from all women, a chip
from soft go and their own chip.
But does not have anything to do with like a broken with 5-spec or any other broken CPUs.
All right.
And then, then we are to this year, it's sci-fi's latest sort of tech demo.
But this time they didn't produce their chip themselves, they had a deal with the Chinese
company S1 who produced this EIC and 770, and they are producing their high-five premium
P550.
This is still the earlier days.
It has an abunter image, but the code for it is unfortunately not quite upstream yet.
And maybe in grey you can see that there's been announcements of all our bots with the
same chip in the future.
So that's my quick rundown of all the hardware we can buy right now.
And for most of them, at least all the ones that are upstream support, they are of course
going to images.
I promise to say this.
So looking forward, one thing I'm looking forward to is, and this is trying again.
This time with their own chip, and they also have their own bot.
And there's also been announcements from deep computing that they might be doing something
with this chip.
So I'm looking forward to this.
Just because it's not like a T-head or a sci-fi call, it's something new.
Then they of course, the known players, Ventana and Reboos, they do a lot of upstream work
so when they finally release their hardware, I'm sure it's going to be great.
But when it happens, I don't want to guess.
And then there's also a few companies that do like PCI cards with a lot, a little, a
risk-fi calls on it for like AI and accelerating stuff.
And I'm sure both of them are thinking about making like a big risk-fi calls, so it can
be like a standalone server.
But when it's going to happen, also, your guess is, as good as mine.
And then, lastly, something I'm looking forward to is that the Chinese Academy of Sciences
is actually developing what they say is an open source, high performance risk-fi process
at the Shanghai.
And I boomers tells me that it's about ready to be taped out, so for something that
you can actually buy and not just for testing.
So I'm looking forward to see how it will perform when it's taken.
Again, you can search for Shanghai and we'll find like this page and links to GitHub and
you can go look at the Urla code action.
That's it.
Did I make it inside?
I can't plan till time.
Because then I have like a little bonus page here with the last one.
Yes, questions.
So did I see that correctly that the most recent non-Chinese course were just micro-ship
and renasas?
No, of course.
Of course, from sci-fi, but chips.
Ah, sorry.
The socks.
Yeah.
Yeah, that's right.
So there is, so currently there are no non-Chinese chip vendors for risk-fifx chips.
Yeah, there's only micro-ship.
All right.
Yeah.
And I think actually they did announce that at least they did announce that they won a bit
for creating space chips from NASA.
So they will be producing more risk-fifx chips in the future.
Yes.
So thank you first of all for the great presentation overview.
Just want to check.
So the vector extension, I can find on the K 230 that you said, but is it 0.7 or 1.0?
That's right.
So when I said the first generation T-head, they had the 0.7 vector extensions and
they were a little, I guess they were, yeah, are we really going to update our GCC and
write all that code?
It's been done eventually to support this because it's only those courses have the
0.7.
Everything else you'd be using 1.2.
Where was it?
So this one has the vector 1.0.
It's, yeah, it doesn't have a lot of RAM and it's not very fast, but it has the vectors.
But then the space midship also has vectors 1.0 and you can write it.
And the p5.0 from sci-fi?
I don't think it has the vector, no unfortunately.
And do you know it has the hypervisor extension?
It does, but they are, it's not advertised because they are not completely to speak.
From the software side, it's not in a window.
So my colleague Heinlek has actually run QMU and have it accelerated.
And for what it tells me it works, but sci-fi tells me that there's something in the hardware
that that's not quite right.
And maybe it's something that can be worked around in software, but I'm not exactly sure about the details yet.
Thank you.
Thank you for the nice overview.
I have a quick question just judging a lot of the companies involved, our Chinese,
is getting sanctioned by being put on the US entity list, actually a concern or a house that happened.
Yes, it is.
What's the risk involved?
Yeah.
So this company is a Chinese company.
They used to do Bitcoin miners and stuff.
And I'm sure they had lots of other projects planned for other RISP-5 SOCs.
Unfortunately, they have been caught with some of their ships on Huawei hardware.
So now they've been put on the sanctioned list.
So they can't similar to how Huawei can't use TSMC,
software can't use TSMC any longer.
So now they have a big problem.
So yeah.
That's unfortunate.
How is the peripheral support and the bugs you showed?
For this one I recommend this one.
It's quite good except for graphics.
Nothing has graphics upstream yet.
So that's also why in my quick.
This one I was saying, I want graphics good luck.
Because if it's not, you need to use the vendor kernel or what you can do is get something like
the on-match spot, which has a really nice PCI driver.
So you can actually just block in an old region card.
And then you get like a problem with this stuff.
What is the state of support in operating systems other than Linux?
Do you have any knowledge of that?
No, I don't know if Jessica's.
She knows about freebies.
I'm sure they also support quite a lot of these tips.
You mentioned for graphics, you can old radion.
Why an old radion?
Sorry.
What I meant was just any PCI card with like an open source driver.
It should work.
No more questions?
Okay.
Sorry.
Have any of the major big free cloud computing providers expressed interest in the risk
of all?
Like Amazon, Google and Microsoft?
I'm sure they're looking at it, but not like anything they said publicly that I know of.
Google has in their Chromebooks.
They have like a security chip.
But that's a microcontroller size chip.
So that actually runs with five.
Not yet.
But I'm sure Reboos and Ventana and Tinstone and they're like,
a lot of companies will want to sell them that.
Once they're ready.
This is a question down here.
So looking at the socks and the additional peripherals.
Are there repositories with open source peripherals in them as well?
Are they located on different dice in most socks?
They're on the same die.
There are also repose with open source peripherals.
So there is a product.
Unfortunately, I forgot it's name, but there is like a product that's some.
A bunch of Python code that will take these designs from different open source.
And then it will like combine it all into one sock.
They have like a risk call.
That's the one I was thinking about.
Okay.
But then I have a design for my own chip that I could tape out if I had like a million dollars too much.
That's right.
Yeah.
Is there a, I mean, really great salt?
Because like what happens when you have your open source design and you go to have it manufactured,
then they will say, oh wait a minute, you actually need to connect all your digital logic to the outside world.
And then you need like a lot of analog stuff that's particular to the process they're using.
And you need to buy that from us and that's completely closed because it's part of their process.
So what is your personal impression on, let's say, hidden vulnerabilities in all of that stuff that you buy adjacent to the actual chip?
I mean, one of the concerns or one of the, one of the reasons that some people have to use risk five are obviously security concerns.
But if I have to buy additional hardware that it's connected to, what does that mean for you?
There's like I called Bonne-Hwang who has a project where he has like a super secure phone.
And he has thought a lot about this sort of security of how can we actually verify that the chips that we,
that we run stuff on actually does what we, what we thought they did.
So what he's done is that he's actually running most of it on an FPGA,
because then it's harder to hide stuff because he can, like they don't know how you dynamically reprogram the FPGA.
So yeah, look up what's the project called with the phone he's making.
I forget. But yeah, Bonne-Hwang, look at that.
Thanks.
Yeah, and I should comment on this.
You know, I'm not the chip designer and I'm starting to get involved with this.
But the designs that we've got that open hardware foundation are fully documented and verified,
at least, you know, for the cores themselves and we've got the microcontroller.
So not Linux class, but that particular macrocontroller as per the shells that are part of it.
But the full set once again, you will have to deal with whatever foundry, you know,
but so maybe you should have a look if you have concerns about things being open and verified at the same time.
I think, yeah.
An openness is a fairly a question, but you have shown a lot of course on the higher end.
Yes, the lower end, the second generation, the second generation,
the second generation, the second generation, the second generation.
That's right.
Yeah, I forgot that disclaimer in the beginning.
I do Linux from my data up, so my view is good to what the stuff that can run Linux.
But it's a whole host of the microcontrollers that also run this file that you can buy.
And it's a really nice, and it's a whole talk on its own.
Yes, and all that out there.
So the question was, yeah, what about the early boot process, I think,
and then like the firmware that runs before we get to Linux?
For now, it's very similar to onboard, so usually they would want you boot.
Even the day is 71-10, even has like the really early boot where it sets up RAM time in
since stuff upstream.
So you basically just run upstream you boot on these stuff, I've chips.
And then you need a component called OpenSBI for technical reasons.
That's also open source, and that's basically it.
Yeah, kind of off topic question, you have a core, you have all digital design,
a lot of analog periphery, when it comes to manufacturing,
how to produce your chips, and how this is financed.
That's a good, who actually produces them?
I think mostly TSMC these days, but I may be wrong, maybe.
Well, at least for some of the designs we've got at OpenSBI Foundation,
we worked with local fondries on getting actual physical chips.
So there's a variety of vendors, but I'm no expert either, so that's anyway.
There's a variety of...
No, in that case it was, I think, in Taiwan?
Yeah.
But it's a question of financing this.
So the financial support comes from foundation, from risk violation,
because you have to pay for it.
Yeah, well, I don't think that the risk violation would bankrupt you
if you were to add chips made, but if you're an academic,
or things like that, then university professors will be able to get a ride
on not fully complete wifers and things like that.
In our case, at OpenSBI Foundation, we had the same kind of deal,
so we had maybe a limited round of 200 chips made from our microcontroller,
and then we discovered there was a short unit, those things happen.
But apart from that, I mean, if you're really in the commercial world,
or trying to get things done yourself, you won't get subsidies for anyone for that,
because manufacturing is quite expensive.
Yes, it's really expensive, and you have to commit, of course,
to use the tooling that they prefer at that particular fundry
and work with the effort for all, so it's not to.
You're baking the kernels for a punter, right?
That's right.
What's special about a risk fight kernel?
So I am sometimes a little more lenient in that I just want to have,
like, about working, so sometimes they take patches before they are fully accepted
upstream, and then other than that, it's just that I re-base of all of the security
patching that goes on and made a bunch of kernels.
So it's pretty much vanilla.
You can pretty much use a vanilla kernel on risk fight.
Oh yeah, yeah.
I mean, depending on the board, right, when for the staff of the board,
yes, and for the two early sci-fi boards, definitely yes,
and the microchip board, and also the all-winner D1,
also works reasonably well.
I have some extra patches that it's not quite upstream yet,
but yeah, for the early board, yes.
What do you use for daily driver and why?
I am. So I also use the staff of the board, so that's just the staff of the board,
the vision-5-2, and I have a milk mask board that I actually use as a jump post in my
Hacker space.
Yeah.
Hi.
Do you have any timeline on the space mid boards,
like when they're going to go upstream?
Because currently they're on that PMB kernel, right?
That's right.
Yeah.
But I forget his name, but DLAN, he's called online,
is working on an upstream again.
And I think they're in, in, when I was short while,
they will have enough that you can run from the onboard EMMC upstream.
I don't think that will take many releases.
But of course, no graphics or anything like that.
So this is more of a ecosystem, I guess,
question. On arm, you have applications like box 86.
What's the situation for running proprietary software,
meant for other architectures on risk-5?
Is there any, like, recompiler emulator like this or not, not really?
Oh, you should ask my colleague, I'm like, you will know all about this.
It does box 86, not have a risk-5 port.
I think there's some, some emulator that does have a risk-5 port.
Yeah.
So when you're building a kernel for a specific sock,
you obviously need something like the device tree overlay
to, to build that correctly.
But how different are the course themselves and what are
the customization points that you have to take into account
when you're building the kernel, when you're, when you're preparing
the kernel to build?
So the little kernel is quite good at sort of patching itself,
once it boots. For example, the first generation T-head course,
they use some bits in the page table in a different way
from, because they used them before the spec was ready.
So the kernel will sort of patch itself and say,
oh, okay, now I'm running on this tip, so I need to use these functions.
So we build what, the kernel is the same.
The only difference is the device tree.
And then once it boots, it will take on on this platform
and it will patch up itself and run.
Okay, so, so you build the kernel just for an abstract,
I-S-A specification and you don't generate that from the
very little code and then you have to build for.
Oh, no, no, no, no, no, no, no, no, no, no, no.
Yeah, just out of curiosity, as you're going to,
how are the kernels actually built? Are they cross-compiled
in the next CD6 board?
Or is it actually, do you have, like, a risk fee farm or something?
I wish, I wish.
But we do have a policy of sort of dog fooding.
So we are not cross, I mean, I cross-compiled all day for testing.
But when we actually release the kernels, they are built
natively.
But by natively, what I mean is that they're built
inside the QMU and big servers.
Yeah, so that's why I'm really looking forward to
when we can actually have a board that has the
virtualization extensions so we can run like virtual machines
on like risk files servers.
Because, yeah, we need that.
Thanks.
Yes, up here.
Is all the hardware that you showed,
64 bit risk files?
Some of it is 32 bit.
Yes, all the boards up in some in about 64 bits.
And all the distributions you will see are compiled for 64 bit.
I think the N2 may have some experimental
where they can compile for 32 bit.
But usually you would do something like
York to a build route for 32 bit.
So it is not possible to run up on 32 bit?
No.
You only have a 64 bit board.
And by the way, there's one similar to other
and microchip made.
If PDA with some risk files costs,
I've also heard about a Chinese FPDA with some 32 bit
risk files costs in hardware.
It's like, first time I've heard
something you actually put 32 bit.
Demiscapable chip in hardware.
Usually 32 bit Linux is when you have an FPDA.
And you just want to use this little of those gates as possible.
Why do you have this policy of not cross compiling?
So I know it's a hassle, but besides that,
why do you do that?
It's just to make sure that everything can compile itself
and everything works as it should.
You know, two chains and all the stuff.
And just to complete on the 32 bit question,
typically you will find 32 bit designs
and you will find 32 bit support for that.
But that's mostly real time operating systems
like Eclipse, Red X or ZIFI.
Hello.
Great to see someone that might be able to answer my question.
So I got a high five on matched board.
And I downloaded Ubuntu.
And it was with 1.2 gigahertz.
Scale down the CPU frequency.
Do you happen to know why?
No, sorry.
But let's talk afterwards.
Yeah, because it was advertised at 1.4.
I think, and it was coming.
Yeah.
So I had to overclock it.
And documentation was not there.
But I managed it.
But you made a book?
Yeah, yeah.
And it works perfectly at 1.4.
Nice.
Yeah.
I just wanted to know.
Yeah.
Let's talk about that.
Okay.
And another question.
When will it be possible to have just one image?
Yeah.
When will possible to have one image?
Yes.
That's a good question.
So,
close the risk-five foundation has this kind of spec that sort of tells how we're supposed to
to boot.
And it leans heavily on quite similar to what others when they're mandating UEFI.
And then hopefully we can live in a world one day where I know UEFI is not perfect,
but at least it's one standard that everybody can use.
And we can just produce images that expect that they are booted using UEFI.
And you don't have to worry about your boot or what's actually running underneath.
Right now there is still, we still need some work to get the information from the UEFI
environment into actually choosing the right device to a boot time.
But that's just a technique I see that we should be able to solve.
But I mean people are working on the same problems in the model.
So we'll probably just slip steam on that.
Yeah, that would be great because also for the maintainers of the OS.
Really bad thing.
And another last question.
The high-five premier P550.
I saw that it has the H extensions.
Yes.
That's it to work.
Yeah.
So that's what I was talking about earlier.
My colleague has tried it out and he got it working.
But it's not really advertised because I'm told that there is some slight hardware issues
where it's not quite up to the final spec.
So maybe we need some software work around or maybe it's not possible.
And not exactly sure the state is, but you can make it work at least.
Yeah, I saw a lot both by 3BSD team with the D-Hive that also made it work somewhere.
Yeah.
Okay.
Looking forward to see something that has gave them enabled.
Yes, me too.
Thanks.
What question based on your personal experience?
So I've seen comments from Qualcomm because it was like that asked for our ISR changes
to build more micro architectural efficient prefetchers.
I guess it was limiting the variance of instruction length.
So you as a software guy did you also come up with some things you found awkward in the ISR specification
that yeah, if you change it like that and that I might have an easier life
or it would be much easier to get you to Linux and channel running.
Not really.
Not something that's not been discussed to many times before and where my opinion has just as many arguments against it.
Just a quick question.
My own experience.
I've got a star 64 board and a couple of rocks here.
Yeah, our board.
So for the same clock speed and number of calls the star 64 seems to be half as performance.
Yeah.
Is that a fundamental hardware thing or is it just optimization?
Is it going to catch up?
So that's also what I was hoping to get out of this is that I want you to understand that.
That because one chip is really slow that not mean that risk 5 is slow.
Like risk 5 is just the PDFs that describe the instructions.
The calls and the size of the twin sisters is usually what matters most in performance.
And I know that for these 1971-10 the memory controller is not as fast as it should be.
So that's maybe why you see that they are like the same clock speed but feels slower.
Hey, thank you for the talk.
This is about CPUIDs like instruction on X86 you have something like that.
I have lately been working on arm. There's nothing like that.
The question is about CPUDiscoverability.
I've learned from a colleague who has been working on risk 5 much longer.
Enable risk 5 and pedora.
Research Jones.
Risk 5 seems to be picking up some of the bad patterns from arm.
And also someone else also in the absolute communities.
Yeah.
That's what we're testing of things.
So people to not make this kind of mistakes.
That's one and CPUID style instruction.
And there's no instruction.
I know there's nothing I've decided.
But we do have, it's called CSRs, like special registers you can read from.
And then you can get the ID of the arms.
But yeah, it doesn't describe the board.
So it's not enough to replace device trees.
It's a bit of a mess on arm.
Like the context is about CPU models.
A bunch of CPU models for QMU.
Enable immigration.
So an arm, it is very tricky to get this.
No such thing as CPU model.
It's like a bag of discreet.
It's a few ID.
Yeah.
So that's it.
Thank you.
In that regard, risk 5 is very much.
Yeah.
Hi.
Thanks for the talk.
I was curious.
If you are aware of any, it is 5 GPUs on the market.
Risk 5 CPUs on the market.
GPUs on the market.
I mean, you can buy a modern Nvidia card.
And it has like three different kinds of risk 5 processors inside.
Like some of them has like a whole operating system running.
Like written in Ada.
Just to manage all the requests it gets.
So you can have like split out your graphics card to virtual machines.
That's a whole talker from on that from the risk 5 conference in Santa Clara last year.
But yeah, it's not something you can directly program yourself.
But if you download the firmware for the Nvidia cards, you can also see that those risk 5 instructions.
Yeah, I was wondering if you were aware about some hardware risk 5 IR advanced data protection implemented.
Oh, there's a news.
Are you talking about a new standard for how the software controller is working?
Yeah, I don't know.
Sorry.
Hello, can you talk a little bit about RA23?
Yes.
All right.
So lastly, I probably should have had a slide on this.
So this is an interesting question.
Because the risk 5 foundation.
In order to manage all these different extensions,
like it'll be really hard to when you're distribution like Ubuntu to figure out which extensions do we actually compile for?
And which don't we?
So the risk 5 foundation has tried to help all of us distributions by making the RVA.
What are they called?
RVA 23 is the latest one.
What are they called specifications or what are they called?
Profiles.
That's the word.
Yes.
And Ubuntu, we have already said that the next LCS relief release will compile everything for RVA 23.
So that means that in order to run the next release of the next LCS release of Ubuntu,
you'll need a chip that has vectors, vector crypto and all the other extensions that are in the RVA 23 profile.
So that means that all the hardware I'm showing you here will not be meant to run the latest LCS release of Ubuntu.
Is the rock hanging waste work that you can buy now?
Nope.
So that's why I'm really hoping that we'll see some hardware for 26 that actually supports the full RVA 23 profile.
But yeah, I mean it's a necessary step because vectors are important for people doing servers and also just graphics for your mobile phone.
So we'll have to upgrade the baseline for a risk 5 at some point.
And we've chosen to do it maybe a bit early, but it's gone, I mean other distributions will have to follow the engine.
And we don't, simply don't have the resources to do like two versions of Ubuntu for a risk 5.
And I take it this target profile also as the virtualization extension or not yet.
Yes.
Yes, that's it.
Thank you.