Hello everyone, my name is Daniel and I'm going to talk about LMAV and how to make open source
chips.
So LMAV is a collection of end-to-end open source risk five microcontrollers and to
end-to-end this context means it's open source from design files to tape-ordered GPRGDS
to files.
It's available in multiple platforms for different applications and those are based on element
names.
So it's just a combination of elements and risk five.
They are fully written in Spinal HDL and they are licensed under the CERN Open Hardware
Language W2.0 and support an FPGA in ASIC flow.
The history of LMAV is tightly coupled to the IHP, the innovations for high performance
microelectronics.
This is an publicly funded research institute in Germany.
They focus on silicon-gaminium electronics.
They operate a small pilot line in Germany, where they produce a research facility
project.
For example, they produce high speed transistors, that's what they focus on.
They're located in Frankfurt, Oda, Germany.
They add two key fundings, a couple of years ago, 130 nanometer open source PDK and
another is free MPW's runs to validate those analog and digital components.
So they had a lot of analog designs but they lacked digital designs for these free MPW
runs.
I already had risk five designs for FPGAs and I also wrote an hyperbus interface for those
so I got asked through connections if I want to port those to make tape out.
And as you can see on this image, this is the first type of LMAV.
It's a flat design, it's the design philosophy, it's pretty conservative, it's an alpha
PDK and the goal was just get bootable silicon.
I received those silicon's last year in February, there was one buck in the hyperbus interface
basically unable to run data and instruction the same time in the external memory.
All other core functions were working and it was the first booting silicon by the HP Open
PDK.
Technically it's the first booting silicon in Europe by the first open source microcontroller.
And the cool thing about this is there's no NDKA required so this is end-to-end open source.
I did a second tape out in April last year, I fixed the hyperbus interface and now it's
actually running Sapphire Atlas, it got an on-share frame, that's the small yellow two bars
on the left bottom left, it got more I-O, more interfaces to silicon proof, it got
a pinmarks controller and a mask I-S because there's a research team in Germany that's
trying to break the mask I-S implementation.
All right, so let's talk about the architecture, this is the nitrogen, the more powerful
platform, it's using a Vex-Rosk 5 CPU, then it's going through and BMP interconnect, this
has an SPI-Exhip controller, so it's communicating to external SPI flash, it has the on-share
frame and hyperbus for external memory and all peripherals are connected through and wish
bone bars and then going through pinmarks to the I-O pad.
All right, so the X-Rosk 5, I think that's a pretty famous of familiar CPU now, it's
a 32-bit Resk 5 CPU, designed in five stages, it's fully written and it's BinLage, the
L, it's actually written by Charles Papon, the maintainer and inventor of SpineLage, the L,
it's a black-in-base architecture, so you can define your CPU with a list of configuration
and plug-ins, and in this architecture has the I-extension, the full integer-base extension,
which is mandatory, has the hardware, multiply and divide, I'm extension, the seek extension
for compressed instructions, so 16-bit instructions and the control and status registers.
All right, so the wish bone, that's actually the biggest change now from the second
from the first two silicon revisions, the hyperbus issue was actually an issue in the
X-C port and X-C4 is a very complicated bus interface, a bus for maybe two complicated
for small microcontrollers.
The specification is also very hard to implement and also to read, there are a lot of people
that actually have questions or problems with that, and the biggest problem is it's an open
specification, but it's still owned by Armlimited, so that's a risk, and the replacement
for X-C4 is now the banana memory bus written by Charles Papon 2, that's a simple command
and request, a channel architecture, so X-C4 for example has five channels, this has only
two, and it's replacing completely the X-C4 crossbar.
The problem is BMP, like X-C4, is a point to point bus, and there's also a requirement
for a new bus for APB-3, and wish bone actually supports shared subordinates or shared slaves,
so a wish bone is the replacement for APB-3, and this is an overview of the bus architectures
on the left side, you can see the instruction and data port, they're going through
in decoder, the hyper bus and the on-ship ramp, they have an arbitrary because both the
instruction and data port have access to those, the data port only has access to the wish
bone, so you cannot read instructions from peripherals, and the data port has no access to
the X-turn SPI flash, because this is right now only read only, speaking of SPI flash,
so this is the, there's an SPI-except controller, it's called, that's for reading from an
X-turn SPI flash, the problem is those have, they have a communication protocol, then
needs to be implemented, so typically that's a command, then you need to send an address,
you might need to send or include dummy cycles, and then you can read or write to an SPI
flash, so in this case this is a dual mode controller, it includes the normal SPI controller
to handle the SPI transaction, and then on top is the SPI-except controller that implements
the SPI-flash protocol, and this time it has also run time switchable I-O protocol, normally
the SPI flashes, they boot in a single bit mode, a standard mode, this controller can
switch to dual or quad mode, so you can increase the, the bandwidth of the SPI-flash,
and then there's also the hyperbus interface, it's mentioned, the problem is that the IP,
the HP is 130 nanometer, so this is SRAM is really expensive in 130 nanometer, external
SRAM devices are very small and very expensive, SRAM on the other side, they are big and
cheap, but they have a quite complex interface, hyperbus, this is in an Octa SPI-like interface,
so this has a very low I-O count, there are only 11 mandatory pins, plus as many chips
selects as wanted, you can connect hyper RAM and hyper flash devices, or RAM is volatile
and flash are non-volatile devices on the same bus, and the throughput is up to 800 megabyte
per seconds, and I don't know if you can see this on this chip, so this is in 64 I-O,
chip on the top, there's a small red, red angle, those are the hyperbus interface I-O,
as you can see one bank is already gone for hyperbus, it's memory only, and on the right
side the blue, this is only SPI, so almost 50% of all chips are gone for external memory and
flash, all right so that's about the architecture, let's talk about the ASIC flow, so this
is a very, very simplified overview, so you need a steering and you also need your design
files, or RTL, then the open flow is using open road, so we're going to convert those
into NGDS to file, then we need to add metal dummy filler, and then at the end we're going
to do the design road check, all right so, the ATWS, they normally only understand very
lock on VHDL, normally they commercial and open source ATWS only understand very lock, for
example, open road is using uses, LMV is written in SPI and HDL, so you cannot feed your
SPI and HDL files directly into the ATWS, but SPI and HDL is a scalar-based framework to
actually generate very lock or VHDL code, and the advantage is that it's a high level
language, so you can actually use modern programming constructs, but you can also use the
entire scalar or Java infrastructure in the background, for example, you can use file
I-O to actually read data from files, all right so next we need a searing or sometimes
it's called guard ring, that is basically just in ring around the entire chip on all
metal layers, and it's to seal off or to guard the chip itself, it has multiple purposes
during the lifetime or the addition during the lifetime of a chip, so first during manufacturing
it's blocking the ionic contamination during manufacturing, then when it's reducing the
mechanical stress when separating dies from the wafer, it's also stopping cracks going into
the core or the chip from the edges, and during lifetime it's preventing getting moisture
into the chip from the outside, from these edges, and as you can see on this image this
is a cup through of the I HP searing, on the bottom that green is the active layer, then
you have five smaller metal layers and two big top metal layers, and in between are just
the vS, all right so next step is generating the GDS, two file, so we have our searing,
we have RTL, you also need a lot of some config files for open road, but when I ignore
this now, anyhow so the first step is convert the RTL into netless, this is done by using
users, for example with open road, then next is doing the splitting the floor plan and
doing the power grid, and again on this image you can see these squares on the other side
those are the band bond pads, then you have the I-O ring, next to them this is for the I-O
voltage rail and the core voltage rail, and then next to them this is on the inside, this
is the power and crowned ring, and in the inside this is the core area, but we're going
to ignore this because that's not placed yet, this is just the I-O ring bond pads, but
the chip is layout so this size is already defined, so the next step is actually building
the core, so first upload we start placing this standard cells on some estimations, then
it will connect those standard cells, or will build the clock tree, like connecting those
to the standard cells, next is we'll do the global and detailed routing between the
standard cells, and finally it's doing a parasitic extraction, so it's getting the RC and
LL use of those traces, and then doing the timing LL analysis, so if those analysis
if they meet the requirements it's done, but normally that's not on the first run, so it's
going, if there are problems with the parasitic or the electric or the timing, then it's
going back to the placement of standard cells, and it's trying to optimize things and
doing all this again, so it's doing a lot of iterations until under no violations are found,
and finally it's doing the physical verification and then do a sign off, and now you can
see now it's actually placing the searing, that's on this image on the outside, I don't
know, you might see this barely, that's this searing here, so now we have our GDS 2 file,
but it's not a production ready, so next we need to add the problem is that we have
going to go back, so you can see on the, for example, the top metal 2, that's what you see
mostly, there are a lot of bond pads, the irons, they have a lot of metal, there are
some power strips on top metal 2, but there's nothing else on top metal 2, so the metal
density is pretty much undisputed over the entire chip right now, and doing chemical, mechanical
polishing, you get a different thickness of those layers, that's a problem because you want
to build next layers on top, and then you have uneven layers, but you also get actually small
electric traces, which means you have unpredictable electrical characteristics, something
you don't want, and the solution is to add, you have to just add dummy metal into the layout,
you can see this again on the top, this is top metal 2, those are really big shapes, and the
idea is, you just calculate a metal density on a tile, for example, HP is using 8 out of
about 800 micrometer, and you get the metal density, HP is also, they define a minimum and maximum
metal density for this layer, and then you try to fill for desired metal density, and then you
get these metal shapes just into the layout, but you can also see there are some layers, they
don't have metal here in this image because they probably have a lot of routing architecture
in the core, so they don't need metal here, but you can also see on the bottom these green and red
overlapping, those are the active and gate pulley layers, also the transistor layers, obviously
you need metal fill, okay the last step is design rule check, there are a lot of maps on this
in this world, some maps in this world, they always have different tools, they have different
experience, they have different, they call this recipes, they also have different process not,
so this is why they always have unique pretty much unique design rules, and they provide this,
but on the other hand you have tools like open road, they cannot check for all design rules,
because they focus on getting a layout, if they were check for all design rules, this would take
too much time, it's very complex, so the last step of doing a tape already design is basically
running design rule checks, and for this example those are the layout rules for top metal
one, I mean top metal is pretty simple, they are so it's a good example, but this has two
important rules, the first one is it's A, it's inside the highest yellowish shape,
so this defines the minimum top metal one with, and that's 1.64 micrometer, the problem is if it's
too narrow you might get disconnected traces or something else, and the other rule is B, that's the top
minimum top metal one space or notch, so that defines the minimum space between two top metal
one shapes, and that's also 1.64 micrometer, the problems if they're close together you get maybe
short-string production, so that's what you want to make sure that doesn't happen,
yeah that's on simple, that's probably the most exhausting step, because if you're two days ahead
of the tape, this is a hard deadline and you have design rules, you question your life
all right, so this is not using make file, it's LMV's using task file to implement this flow,
the flow is basically divided into four steps, so you need to do a task prepared, this is generating
a generating the very lock code from the SpineHDL, it's also generating the open road
config files, et cetera, then it's generating searing macros, the searing macros, next is just
run task layout, then it's starting open road to generate the GDS25, next is doing the task filler,
now it's adding filler, and then at the end it's just task run DSC and it probably takes the most
time to do the DSC check, and that's basically it, so the funding, the HP funding is over,
since December, so they now provide open silicon WMPW shapples now with this open pdk,
it's 1,500 years per square millimeter, but it's only for open source designs, so I think you can
make them actually, but cadence that's fine, but you need to open those designs, you need to upload them
to the GitHub repository, they have three tape audates, this here now in March, the CMOS that's only
digital, and July the CMOS 5L, so this has five metal layers, it has four normal metal layers
and one top metal, and then October the G2, that's where the high speed bipolar transistors,
yeah and if you're interested you can register or this is the same link on the bottom,
if you don't trust Mike you are good, yeah the minimum requirement is actually one square millimeter
as far as I know, so you can actually make pretty cheap chips for research for your hobby projects,
for your company, the only requirement is has to be open source, also yeah, skip one slide,
all right so for all of you, I reserved seven square millimeter on this next to tape out
shuttle or like to do some performance improvements, for example more hyperbuss performance,
adding CPUs to the vectors 5 based on SRAM blocks and also adding more petitions with different
clocks, so these are if you're interested in doing highly high quality images based on your
GDS 2 files, this is a blender GDS is an important blender add-on for importing GDS 2 files directly
into a blender and then you can use blender's cyclic engine to do high quality images based on
like this is using ray tracing and all this computer vision stuff, and obviously LMFU is also
open source so if you're looking for FPGA based microcontrollers while you want to tape out your
own microcontroller, the LMFU is silicon proven, you can use this on the open source,
silicon report box or issues request features, yeah that's basically it free for it to connect
me on several platforms, thank you
you
memory bus
Yeah, so the question was, if I did performance tests on the BMP versus XC4, I did not.
So far, but I was able to improve the chip clock actually, so before I was actually almost
like 55MHz with the IHP, and now it's getting up to 80.
So I get faster clock now, but I haven't checked.
I assume it's not really bad, because I use the SpineLage, the L implementation of XC4,
which has the shared address bus, so it's just for XC, channels instead of 5, so it's
not an official XC4 implementation, but now I'm done.
That was another question yet.
When you get DRC violations, what do you do when you have the C issues, what should you do?
Sometimes you just have to take a look into open roadfiring sample and see if they're
issues in your config, for example, your bond ports, bond paths could be located too close
to the ceiling, then you just need to increase your chip.
We already had an open roadback, but actually made two big metal sheets between
VRs, and the solution was going into the design and manually fix all those, just make
them bigger, because there was only three, like, 30 violations.
Sometimes you just need to fix this, but mostly it's issue with your configuration.
You get more issues when you do an analog design when you draw everything by yourself,
then you get a lot more issues.
And there's one more, and then, yep.
My question is that threats list by is normally having used for PGHM to make, when you
quoted it to an AC, apart, so it has, normally when you're actually doing a V-dab and all
then when you move it, now you start using your own memory cell and, yeah, whatever,
with the hyperbuss and all, apart from that with you, apart from these many of us, the
placement, do you do any changes in the VR-DL design, or do you have to move it?
Okay, the question was, if I did any changes to the V-dab, so far I did not, so right now
it's using, not as, so it's using just standard cells for the registered V-dab, for
example, but I'm working on the cashiest right now based on these S-RAM blocks, because
otherwise it would be too big here, so that trying to do that now.
HP has no S-RAM blocks that are 3 ports, 32 by, what is this? 32? That's the problem.
It's too small for HP.
I was one question here.
I mentioned what, sorry?
Oh, the mask, I don't know, sorry, the question was, if the mask IS is working, I don't
know because the chip is at HP and they're doing the silicon and POSAR right now, the PCB
and POSAR right now, so I hope I get the chip in four weeks.
I think it was one last question.
Which extension?
The question was, if the V-dab's intention is implemented, I don't know, for this
V-dab 5, might be for the new V-dab 5-2, I don't know, I don't have, I don't have it.
I think I might be someone else here with more familiar with V-dab 5, I don't know
right now.
Is that no question?
Do you have time for one question?
All right, yeah.
Which other parts, a PLL, I got the PLL, but there are mixed signal parts on this chip, no.
The question was, if there are mixed signal parts on this design, no, because PIP has no
PLL right now, they're working on this.
I think that's now the another IHP is publicly funded, so this is everything, it's
to be funded and it's a little bit slower, but they're working on a PLL right now and
POSAR and stuff like this, so they're working on analog designs.
They're working on an ADC also right now, so this is all coming now.
This should be for free to part of this open silicon, so you can pick those from the
analog library, but currently not, unfortunately.
All right, thank you again.