So, yeah, it's the topic is a few years in finance, a practical 101 as in 2020-6.
It's an ongoing project and hobby project, so nothing commercial, but important thing is
it's all open source things I'm using it.
Why this project and what are the applications in the financial FPGAs that I'll talk about
that are okay, why basically we would see FPGAs versus CGRAs and if time permits a quick
demo, but yeah, the only good demo is the demo which does not work, let's see if it works,
if it's time permits, why this project, so you know, I mean FPGAs hard and hardware
hard and FPGAs even harder, so the and the other thing is that I witnessed that when
we are talking about the applications we've been running on FPGAs when it comes to finance
they are get kept, so you know, you don't you have access to open source hardware and FPGAs
tools, but still the traditionally the struggle has been the learning curve has you know,
a lot of high for the applications to run on FPGAs when it comes to FPGAs finance applications.
So and how to fix it, so my mental model was that you know, you have to first find out
you know, what are the actual applications and then break down in a Lego approach that
you know, what are the computations being run on FPGAs and the most important part for
me was that you know, which open source projects can be helpful to implement and understand
those computations you know, because that's the spirit of the first and also an open
source community because traditionally Silicon tools has not been open source but now
we have, so why not just see in a hobby project what kind of tools we can use to actually
run those applications which were traditionally very close source and get kept.
So to break it down what we're talking about is, you know, when talked about financial
applications, we mean traditionally this HFT, high frequency trading and then you have
this quantitative workload and you see a block diagram of picture on the right side.
The most common thing is that you know, you have a plumbing pipeline, so regardless
of what kind of applications you have, whether it's HFT or quantitative, you have a plumbing
pipeline which is basically, you know, most FPG-related techniques exist in that plumbing
pipeline and this is what, when I was basically working on those applications in a hobby
project, I found out that you know, okay, if I can somehow deep dive into this plumbing
pipeline, I could see using those tools, understand that what kind of FPGA competitions
you can understand from these tools.
Also when I say you have a small table, what is the difference, you know, like for instance
you have HFT, there is traditionally called ultra-low latency, that's the goal.
In the quantitative is, you don't have the somehow, you know, targeting the low latency,
you can actually throughput.
Workload is likely different in both applications, so you have stream driven, like, you
know, event, event, access stream in a sense and then you have in the quantitative, it's
more badge oriented.
More important part is this control flow, yeah, so you have minimal branching in HFT,
so, but on the other side, the quantitative finance, it's basically branch heavy.
Memory is also important, so in quantitative finance, of course you have, you know,
large error sets, so it's the memory is actually irregular and of the other hand with
HFT, it's predictable, so that is, because it's mostly deterministic workload.
I mean, that's the one background, but the most important part is that, you know, that
is the most basic workflow, which you have in, let's say, in HFT, you know, you have an
exchange server, then you have a data feed, you have the stick data, that is the FPGA side,
and then you have the exchange server, so, to cut, it's very short, so, I mean, to
monologies, take data, that is, you know, a time or a stream of signals, that is basically,
you know, you mutate the market state in hardware, so that is, you know, you can imagine
that stream is coming, it's from the, that is the smart-naked stream, as a stream, you
can say, and then you have a odd basically, that is a hardware generated command packet,
so that is the most basic terminology, which you can summarize in this FPGA part.
So, when I say plumbing HFT, so the most part was that, you know, yeah, that's the, like, you know,
the most, knowledge-get-keeping was mostly on the HFT part. In the next slide, what I would like to
mostly focus on would be that, you know, which tools I have been using to
understand the flow and how that can be implemented on FPGA.
And when I say plumbing HFT, you know, my mental model was that, you know, you have a data feed,
okay, that's fine, that's a stream coming, what else I want to look into that, that, okay,
networking at high-speed I-O, membrane clock timing, these three things like networking,
membrane clock timing, and in this networking, membrane and clock timing, what I would like
to see more inside is that, you know, I mostly, you know, you have a physical silicon, that is
the vendor specific, but then you can go into this mag pipeline, so you have, you know,
plastic buffers and zero buffer design, so you have to really play with the buffers in the mag pipeline.
And then, uh, understandably, the interconnects, you know, uh, the MA Ethernet,
but most important in my experience was that, you know, when you have the timing close and
clock the main, because I'll show you the next slides that, you know, the CDC crossings are
a lot in this pipeline in HFT pipeline, so that is, and we know that, you know, you don't,
you can't actually simulate the clock crossing, so this, this is where the open source tools
becomes useful. And, uh, yeah, membrane subsystem micro-architecture as well, so
also, there are some tools which I will show the next slide, which actually, open source tools,
which, which helps you to actually, uh, unfold or break down the membrane modules on the FGA.
So that is what I was also looking forward in this practice as well. So when I'm talking about
the market error feed was that, you know, I mean, that's the, if I had to start with the tools,
you know, we knew that, you know, the L1 part, which is the, the physical layer, that is the
hard IP, so, you know, that is the proprietary and type of silicon blender, so that's basically
not an open RTL. Uh, what I was basically, most, uh, understandably, uh, more interested was in this
L2L failure, when I had to see, you know, what kind of tools exist, which has open RTL for the
L2 part and, uh, understandably L3, you know, where I can actually see the buffering, minimize buffering part.
And, uh, this, so I actually started with the, uh, tools looking into, which have completely open
RTL, so nothing proprietary. And, uh, even, uh, in L2 layer, you have some vendor tools, which are
still proprietary, but you can customize using, uh, their own tools, but still that does not serve
the purpose. I actually wanted to see what are the actual open RTL where you can play with the,
let's say, this PCSPMA and Mac pipelines. So, uh, I was using mostly, you know, just a background
that, you know, when I started using some open RTL for L2L, uh, AMD's I think, yes, it's, it's, it's,
it's basically a vendor, but their project open NIC is, it's, it's basically open RTL. So, you can
actually, that is also part of my demo with time allows. So, uh, you can actually implement the
Mac part inside the FPGA and you have, you have your own, you, the logic and system very lot.
You can try that, uh, you can generate the, uh, you can simulate that, you can try the different
frequency, like 350 megahertz for ultra scale FPGA and 250 megahertz for also ultra scale.
Net FPGA, I think, most of the people in this room may already know that as an old, uh, I tried it.
I mean, of course, that's something, you know, uh, Net FPGA, it's a very, very powerful platform
for the WordX7 and other FPGAs, but it's somehow outdated, right? I mean, this is, uh, it's a good
to prototype, but it's, uh, having said that, it's basically, yeah, I mean, it's very helpful.
The other tool, which I came across was this SNAT open core. My understanding with open core
was as well, the, uh, the RTL, which exists is around, like, nine, ten years old. So, I don't know
how, I believe in this, that I never tried that. Uh, the most important was this core
and them, and I'm quite sure people in this room already know about core and them, uh, because
that is the, I always say that, you know, we owe a lot to the core and them because that is
the niche open source project, which exists, where you can actually, you know, uh, tailor your RTL
for the L2 and even the L3 layer. And there was also a talk for core and them in first
them, uh, by the main contributor. Also, uh, for me, helpful was that, you know, uh, the video
which existed and also the core work through for the core and them was very helpful.
It's basically, like I mentioned, it's niche, it's complex, uh, using core and them.
And, uh, it's, it's, it's basically an open, uh, it's a nicked platform. So, what I
experienced in last days was that there has been an effort to actually make it more easier to use.
That is basically the FPGA ninja taxi. So, that is the part of the core and them, uh,
core base, but the main team has broken down the complex part of core and them into more
reusable IP. So, that is, and, uh, I can, I can't recall the, the license, but of course,
understand it, it's an open source license. This is one I was, uh, playing with in last weeks
or months. This I mentioned is open nick. Uh, there is, uh, you have, it's, it's completely
based in this system. Very log, uh, RTL. So, you can, I just had a snapshot for the only, like,
QDMA interface, CMAC, and you can put on the, develop your own RTL in the user logic.
It works. So, but what I haven't still done is that, you know, I haven't implemented any
user logic, which is the, uh, trading logic or application financial technology, application in the
open nick as so far now. But, uh, someone who really wants to break down those computations and
understand what's happening inside the, uh, silicon logic, uh, you can use open nick that was,
for me, what it was helpful. That is the corundum. So, that is, uh, I have been using this
taxi platform, but I shared the corundum, uh, yeah, like, oh, high level view because it just tells
you that with the, you can actually find gain control the hardware cues and also, which is important
is that if you, even if you have, uh, like, ultra scale, what it's seven FQJ for AMD or Intel,
you can use that with your own, uh, L2 stack. So, that is basically, I haven't, uh, like, this is,
this is the, uh, I have to mention that this, I have cited from the corundum, um, page as well,
only the page as well. So, that is the, uh, I'm using more on the, this taxi part. So, what I,
because, uh, like I mentioned, corundum is a bit more, uh, complex. So, it does not, uh, I mean,
it's for me, it was an overkill if I had to just run like HFT or, uh, application. So,
luckily, the group has, uh, the contributors of corundum has released this, uh, taxi project,
which is basically, you have reusable IPs in terms of, you know, Ethernet Mac and then you can use the,
uh, XC IPs as well, you can use time stamping. So, what I did was that I took the bear minimum
inside the taxi project, which you had to deal with the L2 and L3 layer, RTL, and, uh,
understandably, cocaTV for the, uh, mainly I'm using cocaTV for the, uh, regression verification.
And, very later, uh, it's also an open source tool, I'm using it for the, uh, more cycle
accurate simulation on the FPGA. So, this is, uh, if someone who is interested into using, you know,
smartnicklyachorundum, and it's complex, so you can actually break down to this tool chain,
you can, uh, really, really get started with the, with the smartnick competitions.
Partying, so, I mean, apart from this, uh, financial terms, what was the most important part when I
started implementing the parsing part inside that architecture, uh, and why, I mean,
I mean, why basically, it's, uh, what is actually common in FPGA is HFT and why I'm using this
exchange native binary protocols, because, you know, the point is that you listen hobby projects.
So, you have a lot of protocols, and for me, it was important that, you know, I need to see,
which is the most, uh, uh, implementable in a less complex way. So, I chose this
exchange native binary protocol, why, because I had, you know, uh, it's understandable, because
I had to see, you know, which has a fixed or semi-fixed binary layout, because I don't want
complex binary layouts, and I wanted to have known schemas, meaning that, you know,
I don't want to really go into the litigated details of the financial application. I just want to
get started on the FPGA. And, uh, yeah, don't dynamic fields that makes the implementation easy,
because, uh, of course, if it's, uh, static, it's easier to, uh, also reconfigure on the FPGA part.
And then the domestic is, because that is common. So, you have to, uh, in any case of parsing,
you, you need, uh, the domestic protocol. So, that's why choose that protocol. Uh, easy to
pipeline and art here. So, that is also that when I was choosing this protocol, I was mostly
interested that, if I have to use this open art here, and if I have to have a POC, which is
implement this exchange native binary protocol, also reduce or have a acceptable, uh, tick to data
latency. I needed an easy protocol so that it's easy to pipeline as well inside the RTL.
So, when I, when we say parsing, so, in most cases, what I understood was that, you know,
what are the core design principles? So, you have this parsing module and what I want to achieve
on the FPGA. So, one thing was that, you know, it has, should we have a zero buffer
cut through? So, meaning that, you know, it's, you know, when you have, uh, the market feed
feeding on the FPGA. So, you need the data optimized for the field extraction. This is what I was
targeting, and then, uh, what I wanted to more as well, that I mentioned last slide was that
pipeline determinism, that, you know, I need to have this fixed latency execution part. So,
I want, this was the one core principle I was targeting on that, uh, on the FPGA implementation.
So, it's mostly streaming, not mostly always streaming. So, it's the pipeline FSM's,
when it's, uh, in any parsing, it would be pipeline FSM's, and the bell shifter. So, that is,
was the most, uh, common, uh, computation when, uh, using this parsing. So, you have this, you know,
for this, uh, realignment within the access to me bus. So, this is was when I was, uh, using this
RTL, open RTL, I had this thing, okay. When I have to implement the parsing part. So,
I need this, uh, multi-stage, you know, bell shifters. So, because it helps you for this,
so-called dynamic fixed realignment. So, that was the one parsing part.
This is the parser FSM. So, I mean, it's, like, uh, most common FSM. So, you have basically,
it starts getting the payload, and then you have, you, you get the byte inside the parsing module
from the network part, and then it detects, you know, what type of message is it, and, uh, you have
a common, uh, messes protocols like, you know, you can cancel add, add message. So, that is implemented
inside the, the parsing module, which is facing integrating with the L2 layer. So, I took this
image because that is, uh, also an HFT accelerator project, which I, uh, the use and RTL, open source
RTL. So, just understand, you know, what kind of FSM, what, what is the state machine inside that,
the, what kind of state machine is that in the, the parsing module.
Uh, memory parts. So, uh, when it comes to this autoboke, well, there's only one main data structure,
which actually affects your, you know, latency. So, what is mostly you're dealing is, we're dealing
with this memory and combinational, combinational logic, you know. So, you have, uh, pipeline and streaming.
So, in most cases, which I can, we shall show the next slide is that, you know, it's the B-RAM.
So, you, you, you play with most B-RAM because that is, uh, more than enough. And when I mentioned
membrane combinational, combinational logic, meaning that is, that is the, understandably,
the two basic things, which you're dealing on the, on the FPGA silicon, when it comes to order
book architecture. Uh, yeah, like I mentioned, that is the, uh, on chip B-RAM memory, mostly playing
with B-RAM. You can also use ultra-RAM, uh, but that is, when the specific, so not every FPGA
using the ultra-RAM. So, when it comes to, memory, mostly is, they're using B-RAMs. And,
S-P-M-N overkill, because we're not bound by the capacity inside the order module. So, that is,
uh, you can, you can implement, you can do anything with B-RAM for all order books.
Uh, since we are running out of time. So, yeah, actually this is one project, which is,
which dates back to 2016, 2017, uh, they implemented the complete tool chain, except the, I think,
uh, the Ethernet part inside, uh, C++ high level synthesis. So, what I have been doing recently
was that, you know, that project was implemented around 2016, 2017. So, what I do now is that,
I try to use some, uh, other compiler optimization, which were not existing at that time,
to see if we can achieve better latency in this pipeline. So, this is one part, which I actually
wanted to show in the code walkthrough, but yeah, I can also make a video later on and put it there.
So, when I mentioned the beginning of the talk that, you know, what kind of,
uh, open source, maybe modules, I was, I was looking into, I mean, I did not use, uh,
so far anything, uh, regarding the B-RAM or maybe modules, but I found out falling projects,
which were really interesting to see, you know, how you can use these,
a couple of projects, which has, uh, memory modules to have, for instance, uh, you know,
you can implement memory banks where traditionally you are dependent on the proprietary tools.
So, yeah, I think there can't, time is up, so because, uh, timing closer. So, that is the,
mostly tools, which I was using, a hard problem. This is what I'm following tools, which I was using
for the CDC tools. So, that's it. Yeah, the last thing is that I have been actually fixing a box
in one, uh, open source tool, which is from the AMD, but that's open source. So, what I mean,
actually doing is that in this tool is that to make it easier for the users to use, because
if you go into this project, you'll find out that it's, it's, it's really tough to even get started.
So, this is what I wanted to show as well in, in a demo, but yeah, I can actually, it's on the
GitHub. So, I'll release that, you can, you can see that. That's it. Yeah. Thank you.