Okay, hi, hi everybody, approaching to the end of the post, and today I'm going to update the
talk I did it in back in the web procedure, can we run back in Tokyo, I did a similar talk
there, I think most of the guys here in Europe, my lobby attend that conference, I'm going
to repeat it, although it's online, but also we give some updates, it's the two months
talk in the December now, it's one month, and then we make it a lot of great progress.
So today's talk is all about picking the record, how to we get, we spy, upstreaming
to in better than any other of the ISA and trying to match of the X86 as much as we can.
And I'm feeling, I'm the flunked up, but deep computing, so actually I'm a software guy, before I
I unknow my money from software, and I star, I'm VM guy and compiler guys, I put a most of the VM
from old age, I already am older to JavaScript, to old adult go, whatever VM I put most of the stuff,
and I also started compiler guy, I familiar with all, in back in the old age, the MIPS compiler
opens it for, so I'm the founder of the computing, I found the company hardware company in
Co-Wick, and I'm very serious software guy, I understand where Alan Key says that, so I don't
know the money from software and losing all in hardware, it's very good.
So, and I make Naptop, this file laptops, so this is the 2003 and we make the most expensive
wrist file laptop in the world, now is in museums, so it's $5,000, and yeah, we didn't make them up,
but 100 pieces, hopefully, is the Pentate N, and then in 2004, I make a very affordable
second generation of laptop, we have A core, and then that's separate, as well.
So, I stuff in and out, and the first ever time, you went to a federal account, if I support,
and that's the beauty of a wrist file, and after a while, I started thinking about, I only care about
wrist file, I don't care about battery, I don't care about screen, I don't care about everything else,
keyboard, on the hardware, so when I do laptop, I stuff in and out that, I lose so much money on the
rest of the things, nothing to do with the wrist file, and I stuff like that with framework, so they have
a booth there, so you can see, they have a laptop and support multiple architecture, I think you
guys should know about it, if you want to do kernel, you can port all different architecture from
xxx to arm to this file, they won machine, you can support all the architecture with different
motherboards, so do, do, do, do, do, do, take a look, and then, and although it's nothing to do,
kernel, I would soon pass it by this, basically it's very good for our European cultures,
so it's DIY, fix it yourself, last forever, very monumental, so, and then I did the first
aroma, a framework, motherboards for them, the same fork hole is around 150 dollars, 80 grams,
but now we move about probably 200 dollars, because DDR, price cannot crazy, so, and then as you
mimic a Nala ball, with 64 DDR, and it double the price now, if or whoever buy the first patch,
you already get rich, so, and much, and now two months, two months ahead of the mass production,
so now we get a 16-core, two one-by-gigahertz, and it's a pretty usable list file now, so everyone
won the kernel should help on this file kernel, and you will write the height, because I didn't
this file kernel need more help than any other architect, and the architectures, so, for ARM,
I've got a lot of money, ARM have a lot of money, they have a lot of people, I'm working the kernel
by for this file, we don't, so, now, back to the state, we'll talk about why this file
and upstream main, the differences, so, for ARM, whatever ARM, SOC come out,
they will sell meanings, so they don't really care about human, why should they care,
right, their SOC value, and then, and for this file, it's really bad, because, for Rau,
the risk file, the whole SOC where, from the kernel to 2-chain, to upper stack,
whatever, it's not optimized, because the hardware is not there yet, so SOC won't catch up,
so, for us, looking at hardware, I have a very funny experience, the three years ago,
my 4-core machine running dead-time, the damn bin, is very slow, but now running damn bin 13,
it's much more faster, it's bizarre, all right, the reason why it's because,
this file software is better and better, similar, so that means I wish for hardware,
it has to leave a very long silicon on time, so that demands more upstream main needs to be
the need of long time, so that's why I would say that compared to ARM,
we specify it desperately need upstream main, more than any other architecture,
and then the other thing is that all the SOC guy, including myself, I'm making a motherboard,
I have to guarantee the mass production, so I only allowed to work on LKS,
because if you use upstream cano, the main 9, I know idea where the problem is, it's so freaky,
if it gives me a 6-tock 20, if you're not LTS, I'm scared,
because I know idea where the hardware, the hardware, so that is the hardware parameter, I'm saying
that we have to work on LTS, but at the time we work on LTS guarantee the mass production quality,
and then we off the track, we off the main 9, probably, I remember I gave my Roma second,
left up to quite KH, I have seen, can you help me to upstream everything? It said,
you don't, you have 100 or what, 60,000 nine of code change, no chance,
is that even then this can't do that, but anyway, so that, that is the pain of it, so,
and I think there's two methodology, we got the company wrong, because from over our SOC guy,
at the mass production guy, we still inherit a lot of habit for ARM,
which we work on LTS, but in fact, we should work on the post same as X86, we work on
main 9 and back port to LTS, but that is the wrong thing we have done, so, and I give you
your status, so now I give you to the first generation motherboard status, and it's where funny,
I'm not sure you guys can see it, the old PowerPoint, and then 2018, we got the IP,
and then SOC will four years later, we get it into the SOC, and then I take another two years
to get into my motherboard, so it's 60 years, so, but you need to find out, take a look at
the upstream progress, our SOC is the first, when upstream is back in 2023, it's painful, it's low,
so, and according to a QRKH, there's a one thing to do, okay, this has done the upstream
means since FPGA evaluation, revocations, so the mass patch, I still ongoing, 30 spray with GPU
stuff related, so we know, right, mean this, we know we can solve the GPU saga, mean this kind,
no one else can, and that's it, and then average the upstreaming, and another thing is that we
let go of experience of upstreaming, so it takes 10 rounds, ping-pong, 10 rounds, so it's a bit one patch,
okay, this first motherboard, it's pretty much the upstreaming, okay, and then the second one
is even more awful, the CPU IP is related, absolutely means not even done yet, since the IP
introduced in 2020, so that's the one thing to do, okay, so how are we going to do better, so I
forced all my SOC guide to do more upstreaming, and we spied the two better, and graph says that as
well, so this is the work work back in 2020, the 2008 says that you need to upstream
stuff from the simulations, right, that's x86 away, I'm the end to it, right, so it's actually 15 years
ago, 20 years ago, so experience, so, and how do we do it, so basically, I forced my the first
generation motherboard SOC guide, I said you had to upstream before the chip comes back, and and we
and actually is scary, because of all our engineer, even have experience, is arm cultures,
the race scale, the level that it before, so, and and a lot of things as well, even the main
time that we concern, you don't have hardware, should I allow you to submit it, so that there's a problem,
and the approach, we do it the simple one first, Pintential, or majority of the CPU IP related
first, FBJ before, then we do it easier to difficult, that's the way we do it on the K3,
so, and how's the progress, so we do meet a few surprise, during the process of it, before,
during the FBJ verification, and the tip out before the chip comes back, the three months will be
a lot of surprise, so first thing, we realize that people look at the call, if we do in the
corner, then we know we stray way, know what's the problem of the call, decide how we're designed,
we call it, but a little asymmetry, that means they have mixed up, mixed cluster,
RV-25, one RV-25, and they have different RVV, and and I have AI customer instruction in one,
so to the software point of view, I still remember Quest email to me, it's a unit,
the school up, you should let me know this diagram nine months ago, basics is very painful to get
upstream, and software support, so and besides that, we have some DMA zone easier as well for the
two-peck, and then the other thing is that when we start the silicon upstreamming, we do
share a lot of co-out for all the community guys, so initially I invite people to a private,
private repository to look at our call, we scale off with this closer or the hardware information
before the product announced, but and then at the end I mean to convince the associate
guys that we have nothing to lose, it's bad enough, let's open it up, let the world say it,
so that's why we open source everything, first-ever open source everything before the chip comes out,
so and then we do pick a few moves, the FPG target, so we make the wrong target, we separate the
patch, people refuse it, and then we, we, we didn't go for any of the most of the testing,
we just do upstreaming without testing it, so it's very brave, and, and yes, when in reputation
ruined, according to Grasse, nothing wrong, we just fix it if there's a bug, right, nothing
shamed about it, so that's what, not the progress is, so what can we improve it, and then
I will say that, we still can do better, especially one for all the CPU features, we can do a lot of
better, so so far we, I forgot to bring the board, it can feel free to come down to our both,
we already have the latest chip with the manufacturer sample board working, and then we still have
found some major CPU features, it doesn't work, for similar hypervisor, actually we should
turn all those software back in the FPGA stage, we haven't done all the replication, also,
we have to, we have seen that, for some AI features, we still haven't got it working,
we should turn that back in the FPGA replication at that time, and also upstream in at that time,
then we pretty much get everything ready, but now we haven't got it, so there's still a lot
of things to improve, and of course now we learn, SOC, you have to have consistency, we use as many
as you can, so, for space mid, the K3 and K1, they have shared majority of the 60%, 70,
they are the same IP, so all those upstreaming effort for K1, and we use most of the upstream
effort from K1 anyway, so it's much more faster, so that's all for the day's talk, so,
and this first ever, I think we have done better than now, including Qualcomm, and we continue
to do better, for less chip, for the test server chip, and because it's less IP in both, and
look forward to you guys' help, and especially we read it in RIS5B, a lot of enough resources.
Thank you, thank you, thank you guys, yeah, you can go up to the GitHub and take our upstream
patches, it's not done by me, done by the SOC guide, but they were great.
Any questions?
Yeah, hi, thank you for your talk, regarding upstreaming the data sheets of all these processes
that are you interested in to go upstream, is it easily available for download?
Yes, we are aware that one to have our upstream, we release all the data sheet, and it
includes our schematic, all right, thank you, we have to do better than then now, I have no
CPC, we should have no CPC, we should have no CPC, we should have no CPC, we should have no CPC.
Other questions?
So, do come up to the upstream canal log, we did pretty well, actually, the SOC guide did about 10
patches before the chip comes back, where they walks a lot, I don't know.
Not really a question, but more for our comments, so we have TH5020, we have SLC at scale
way, and we have to maintain an all fork of the canal because of that, because of the lag of
the upstreaming, so I think upstream batch may line, it's something that will benefit all of us.
Definitely, we will upstream as much as we can, except the GPU, GPU, I can't deal with it now.
I've no experience from working on a CPU, but working up from a device I've been made quite a
good experience by implementing it in Qemu, and doing a software simulation, and then we had
driver stuff and so on, pretty good shape when we had they have already. I don't know how it works
out for this five, probably it's too complicated. I think it's rare complicated, because I think using
simulator, same as I'm a VM guide, usually I do, similar to first, before I touch the hardware,
otherwise it's too pretty, but we think that because so much peripherals, we have to code that,
we have to code that, we have to code that, we have to code that, we have to code that, we have to
do many math. So the only one we can emulate, majority of the CPU features, okay, I have a
wiser, blah, blah, blah, blah, blah, blah, and AI, those things, okay, she's going to simulator,
and they start upstreaming, and then the FPGA, and then also as well, so that we should do better
seriously, but the rest of the code that the I.O. and need to do hardware, all right,
CPU user would definitely even do better. Thank you. All right, out of time, thank you.
Thank you very much, thank you.